US4518868A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Superconductive large-scale integrated circuit chip
Assignee: Hitachi Ltd
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Filing: 1981-06-29
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Granted: 1985-05-21
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Expires: 2001-06-29
Abstract
Abstract A superconductive large-scale integrated circuit chip comprises a plurality of pads, a superconductive line which short-circuits respectively adjacent pairs of the pads, and an input buffer circuit. The input buffer circuit includes a Josephson junction which is either in a superconducting state or a finite voltage state in response to a magnetic field established by current that is supplied to the superconductive line by flowing in from one of the two pads and flowing out from the other pad. The input buffer circuit wave-shapes the externally supplied signal into an amplitude-controlled signal, and the latter signal is led by a superconductive line to a circuit within the chip which requires the signal. Even when the external signal current has become abnormally great due to noise, etc., any circuit situated halfway within the chip can be prevented from malfunctioning from the magnetic flux generated by the large current.
Inventors
- 👤 Yutaka Harada
- 👤 Kunio Yamashita
- 👤 Nobuo Kotera
- 👤 Hirotoshi Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 08:18
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/92; H10; H10N; H10N60/00; H10N60/80; H10N60/805; H10N69/00; Y; Y10; Y10S; Y10S505/00; Y10S505/825; Y10S505/856; Y10S505/857; Y10S505/865
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
237 words
A combination of a plurality of superconductive large-scale integrated circuit chips, each comprising: a plurality of conductive pads which are disposed along at least one of peripheral edges of said chip; an input superconductive line which short-circuits a pair of said plurality of pads; an input buffer magnetically coupled to said input superconductive line, said input buffer including a Josephson device which operates in a superconductive state when no current flows through said input superconductive line and in a voltage state when current flows through the input superconductive line, wherein said input buffer further comprises means coupled between the Josephson device and a predetermined circuit in the chip for controlling the application of current to said predetermined circuit in accordance with the state of operation of the Josephson device; an output superconductive line with the chip coupled to receive an output from the predetermined circuit within the chip so that current flows in said output superconductive line when the predetermined circuit produces an output; an output buffer magnetically coupled to the output superconductive line, wherein the output buffer includes a Josephson device which operates in a superconductive state when no current flows through the output superconductive line and in a voltage state when the current flows through the output superconductive line, wherein an output buffer at least one of said superconductive chips is coupled in series to input superconductive lines of at least two other superconductive chips.
Claim 2
Dependent Claim
237 words
A combination of a plurality of superconductive large-scale integrated circuit chips, each comprising: a plurality of conductive pads which are disposed along at least one of peripheral edges of said chip; an input superconductive line which short-circuits a pair of said plurality of pads; an input buffer magnetically coupled to said input superconductive line, said input buffer including a Josephson device which operates in a superconductive state when no current flows through said input superconductive line and in a voltage state when current flows through the input superconductive line, wherein said input buffer further comprises means coupled between the Josephson device and a predetermined circuit in the chip for controlling the application of current to said predetermined circuit in accordance with the state of operation of the Josephson device; an output superconductive line with the chip coupled to receive an output from the predetermined circuit within the chip so that current flows in said output superconductive line when the predetermined circuit produces an output; an output buffer magnetically coupled to the output superconductive line, wherein the output buffer includes a Josephson device which operates in a superconductive state when no current flows through the output superconductive line and in a voltage state when the current flows through the output superconductive line, wherein an output buffer at least one of said superconductive chips is coupled in series to input superconductive lines of at least two other superconductive chips.
Claim 3
Dependent Claim
50 words
A superconductive large-scale integrated circuit chip according to claim 1, wherein a terminating resistor is connected in series with the series connection of the input superconductive lines of said at least two other superconductive chips, said terminating resistor being located outside of the superconductive chips to which it is connected.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-05-20 | 1988-11-19 | 1989-05-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-05-20 | 1992-11-19 | 1993-05-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-05-20 | 1996-11-19 | 1997-05-21 | $7700.00 | Window Closed / Lapsed |