High frequency inverter

Claim 2

In an uninterruptible power supply which includes a main source of A.C. signals for operating a load, an inverter circuit for outputting auxiliary A.C. signals to the load comprising: a source of reference A.C. signals; pulse width modulating means connected to the output of the inverter circuit and the source of reference A.C. signals for comparing the auxiliary A.C. signal of the inverter circuit transmitted to the load with the reference A.C. signals to output a plurality of clock signals modulated in accordance with the voltage difference between the signals; a D.C. source; first switching means connected to said D.C. source and said modulating means and operated by said modulated clock signals to output a plurality of auxiliary A.C. signals when enabled; a source of control signals transmitted to said first switching means for enabling said switching means upon failure of the main source to supply A.C. signals to the load; second switching means connected to the load, said modulating means and said first switching means for transmitting the auxiliary A.C. signals to the load and said modulating means when enabled; a source of system clock signals; and control means connected to said second switching means and operated by said system clock signals for enabling said second switching means in association with said system clock signals whereby said second switching means will output the auxiliary A.C. signals to the load and said modulating means.

Claim 3

The inverter circuit of claim 1 in which the modulated clock signals outputted by said modulating means comprises the first and second oppositely phased clock signals and said first and second switching means includes first and second switching members each receiving one of said oppositely phased clock signals whereby the first switching members will output a first portion of the auxiliary A.C. signals and the second switching members will output a second portion of the auxiliary A.C. signals.

Claim 4

The inverter circuit of claim 2 in which said first switching means includes a first transformer means connected to said D.C. source and said first switching members of said first and second switching means and a second transformer means connected to said D.C. source and said second members of said first and second switching means for transmitting said oppositely phased clock signals between said first and second switching members, said second switching means being connected to a mid portion of the transformer means to transmit a portion of the auxiliary A.C. signal when operated.

Claim 5

The inverter circuit of claim 3 in which said first and second switching members each comprise a metal oxide semiconductor field effect transistor.

Claim 6

The inverter circuit of claim 3 in which said control means includes first gating means receiving said system clock signals for outputting first and second oppositely phased system clock signals, said gating means connected to said first and second switching members of said second switching means enabling said first switching member to output a first portion of the auxiliary A.C. signals and the second switching member to output a second portion of the auxiliary A.C. signal.

Claim 7

The inverter circuit of claim 5 which further includes second gating means connected to said modulating means and said first gating means for outputting said first and second oppositely phased clock signals to said first and second switching member of said first switching means in response to receiving said first and second oppositely phased system clock signals.

Claim 8

The inverter circuit of claim 6 in which said control means further include third transformer means connected to said first gating means and said first and second switching members of said second switching means for outputting said first and second oppositely phased system clock signals to said switching members enabling said switching members to output a first and second portion of the auxiliary A.C. signals to the load.

Claim 9

In an uninterruptible power supply which includes a main source of A.C. signals for operating a load, an inverter circuit for outputting auxiliary A.C. signals to the load comprising: a source of reference A.C. signals; pulse width modulating means connected to the output of the inverter circuit and receiving said reference A.C. signals for comparing the auxiliary A.C. signals and the reference A.C. signals and outputting a plurality of high frequency clock signals modulated in accordance with the voltage difference between the signals; a D.C. source; first switching means including a pair of first and second transistors connected to said modulating means, said transistors outputting said high frequency clock signals when enabled; a source of first control signals transmitted to said first switching means for enabling said transistors upon failure of the main source to supply A.C. signals to the load; a first transformer member connected to said pair of first transistors and said D.C. source to output a first portion of the auxiliary A.C. signals; a second transformer member connected to said pair of second transistors and said D.C. source to output a second portion of the auxiliary A.C. signals; a source of system clock signals; second switching means connected to said first and second transformer members for outputting the first and second portions of the auxiliary A.C. signals to the load when enabled; and control means connected to said second switching means and operated by said system clock signals for enabling said switching means in accordance with said system clock signals whereby said second switching means will output the auxiliary A.C. signals to the load.

Claim 10

In an uninterruptible power supply which includes a main source of A.C. signals for operating a load, an inverter circuit for outputting auxiliary A.C. signals to the load comprising: a source of reference A.C. signals; pulse width modulating means connected to the output of the inverter circuit and receiving said reference A.C. signals for comparing the auxiliary A.C. signals and the reference A.C. signals and outputting a plurality of high frequency clock signals modulated in accordance with the voltage difference between the signals; a D.C. source; first switching means including a pair of first and second transistors connected to said modulating means, said transistors outputting said high frequency clock signals when enabled; a source of first control signals transmitted to said first switching means for enabling said transistors upon failure of the main source to supply A.C. signals to the load; a first transformer member connected to said pair of first transistors and said D.C. source to output a first portion of the auxiliary A.C. signals; a second transformer member connected to said pair of second transistors and said D.C. source to output a second portion of the auxiliary A.C. signals; a source of system clock signals; second switching means connected to said first and second transformer members for outputting the first and second portions of the auxiliary A.C. signals to the load when enabled; and control means connected to said second switching means and operated by said system clock signals for enabling said switching means in accordance with said system clock signals whereby said second switching means will output the auxiliary A.C. signals to the load.

Claim 11

The inverter circuit of claim 8 in which the high frequency clock signals outputted by said modulating means comprise first and second oppositely phased high frequency clock signals and said first switching means further includes first gating means connected to said modulating means and said control means for outputting said first and second oppositely phased high frequency clock signals to said first and second transistors in response to the operation of said control means.

Claim 12

The inverter circuit of claim 9 in which the first switching means further includes first drive means connected to said first gating means and said first and second transistors, said drive means enabled by said first control signals to output said first and second oppositely phased high frequency clock signals to said first and second transistors.

Claim 13

The inverter circuit of claim 10 in which said second switching means comprises a third transistor connected to said first transformer members and a fourth transistor connected to said second transformer member, said third and fourth transistors connected to said control means and operated in response to the operation of said control means to output the auxiliary A.C. signals to the load.

Claim 14

The inverter circuit of claim 11 in which said first, second, third and fourth transistors are metal oxide semiconductor field effect transistors.

Claim 15

The inverter circuit of claim 12 in which said control means includes second gating means connected to said first gating means and said third and fourth transistors and receiving said system clock signals for outputting first and, second oppositely phased system clock signals enabling the operation of the first gating means and the third transistor to output a first portion of the auxiliary A.C. signal and the fourth transistor to output a second portion of the auxiliary A.C. signal.

Claim 16

The inverter circuit of claim 13 in which said control means further includes second drive means connected to said second gating means for outputting said first and second oppositely phased system clock signals and a third transformer member connected to said second drive means and said third and fourth transistors for outputting the said first and second oppositely phased system clock signals whereby said third and fourth transistors are alternatively operated to output the first and second portions of the auxiliary A.C. signals to the load.

Claim 17

The inverter circuit of claim 14 in which said third transformer member includes a first secondary winding connected to the gate electrode of said third transistor and a second secondary winding connected to the gate electrode of said fourth transistor enabling the transistors for operation in response to the third transformer member receiving said first and second oppositely phased system clock signals, said first transformer member having a secondary winding including a mid portion connected to the source electrode of the third transistor and said second transformer having a secondary winding including a mid portion connected to the source electrode of the fourth transistor whereby the third transistor will output a first portion off the auxiliary A.C. signal in response to receiving a first oppositely phased system clock signal and the fourth transistor outputting a second portion of the auxiliary A.C. signal in response to receiving a second oppositely phased system clock signal.