Entity control for raster displays

Claim 2

Apparatus for carrying out displayed feature detection and verification in a raster system including, a store for items of data, display means for serially receiving incoming items of data from said store, and forming an image therefrom, each item of data being used to form a part of a feature of the image and being provided with an identifying signal associated with the feature formed in part by said item, input means for generating signals, each representing the coordinates of a selected point in the feature formed in part by said item, first comparison means for comparing the signal representing the coordinates of the selected point with the incoming items of data from the store to indicate if a correlation exists, and providing a loading signal if such correlation exists, register means for receiving the loading signal of said first comparison means, and in response to the loading signal storing the identifying signal of the item of data so compared, second comparison means for comparing the stored identifying signal with the identifying signal of the serially received items of data from said store, and means coupled to the second comparison means, for emphasizing the feaure of the image correlated with the selected point, said second comparison means providing a signal to said emphasizing means for emphasizing the feature when a correlation occurs between the stored identifying signal and the identifying signal of the received items of data from the store.

Claim 3

The apparatus of claim 1 wherein said register means includes; means for detecting and verifying items of data from said store, means for latching the identifying signal from each item of data received from said store so long as a loading signal is received from said first comparison means, and means for resetting said means for latching the identifying signal when the loading signal is no longer received from the first comparison means.

Claim 4

The apparatus of claim 2 wherein said input means includes a graphical input device.

Claim 5

The apparatus of claim 3 wherein said display means includes a cathode ray tube, and refresh means are provided for causing the store to pass items of data for a display repeatedly.

Claim 6

The apparatus of claim 2 wherein said display means includes a cathode ray tube and said input means comprises means for indicating selected points on said tube including a continuously refreshed cursor and means forming said cursor.

Claim 7

The apparatus of claim 2 wherein the means for emphasizing portions of the display does so by changing the color of the emphasized portion in relation to the rest of the display.

Claim 8

The apparatus of claim 2 wherein the means for emphasizing portions of the display does so by changing the brightness of the emphasized portion in relation to the rest of the display.

Claim 9

The apparatus of claim 1 wherein said register means comprises; first and second random access memory means having inputs coupled to said data store and having respective outputs, first and second AND circuits, each having respective first and second inputs, a register latch, a clock, and a control logic circuit driven by said clock, said first memory means containing the entity detectability status of the input data from said store and having its output coupled to the first input of said first AND circuit, said first AND circuit having its second input coupled to said first comparison means and its output coupled to said clock driven control logic circuit, said control logic circuit being further coupled to a vertical synchronization circuit and to a register latch and to a second AND circuit, said control logic circuit providing a set signal to said register latch to latch the identifying signal of the selected item of data upon coincidence of signals from said clock and said first AND circuit, said control logic circuit providing a reset signal to the first input of said second AND circuit upon receipt of a signal from said vertical synchronizer circuit, said second memory means containing a verification mode of the input data from said store and having its output coupled to the second input of said second AND circuit, said second AND circuit passing a reset signal to said register latch to unlatch said latched identity bit upon coincidence of said reset signal from said control logic circuit on a verification mode output from said second memory means.