US4516218A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory system with single command selective sequential accessing of predetermined pluralities of data locations
Assignee: Texas Instruments Inc
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Filing: 1980-06-26
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Granted: 1985-05-07
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Expires: 2000-06-26
Abstract
Abstract This addressing system, advantageously for smaller scale data processors with relatively narrow data paths, facilitates transferring pluralities of multibit data words, e.g., storing or fetching the contents of a multidigit register in a calculator. A bidirectional bus couples a controller and a plug-in memory. The controller generates address, data, and command signals. A decoder receives command signals and outputs signals to a program counter (PC) alternatively indicating a normal mode, in which the controller accesses a single specified memory address, or a multiple access mode, in which a predetermined number of sequential addresses are accessed starting at a specified address. In response to selective command decoder output, the PC alternatively may store received addresses, output stored count values to the controller or to a memory array, or increment the count value in synchronism with data transfers to/from multiple memory locations. The decoder, PC, and memory array are contained within the portable memory module's housing, which may be mounted in another housing containing the controller. In a ROM embodiment, the mounted memory is powered directly from a source in the controller housing. In a RAM embodiment, the module's housing includes a power switching circuit and an internal battery to provide uninterrupted power to the read/write memory cells irrespective of whether the module is mounted or detached.
Inventors
- 👤 Stephen P. Hamilton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 09:15
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/3004; G06F9/30043; G06F1/00; G11; G11C; G11C5/00; G11C5/14; G11C5/141
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
233 words
A memory system comprising: a bidirectional bus means coupled to a source for providing command signals, address signals and data signals; a command decode means coupled to said bus means for generating respective first, second and at least a third decode outputs in response to receipt of first, second and at least a third command signals; a program counter means coupled to said bus means and to said command decode means for storing therein an address corresponding to an address signal received via said bus means upon receipt of said first decode output, for generating an address signal corresponding to said address stored therein upon receipt of said second decode output, and for sequentially and repetitively generating an address signal corresponding to said address stored therein and incrementing said address stored therein upon receipt of said third decode output, this sequential and repetitive operation being repeated a predetermined number of times corresponding to said third command signal; and a memory array coupled to said bus means, said command decode means and said program counter means, having a plurality of multibit data words stored at memory locations therein corresponding to said address signals, for providing multibit data words as data signals to said bus means upon receipt of said address signals from said program counter means in response to either said second decode output or said third decode output from said command decode means.
Claim 2
Dependent Claim
233 words
A memory system comprising: a bidirectional bus means coupled to a source for providing command signals, address signals and data signals; a command decode means coupled to said bus means for generating respective first, second and at least a third decode outputs in response to receipt of first, second and at least a third command signals; a program counter means coupled to said bus means and to said command decode means for storing therein an address corresponding to an address signal received via said bus means upon receipt of said first decode output, for generating an address signal corresponding to said address stored therein upon receipt of said second decode output, and for sequentially and repetitively generating an address signal corresponding to said address stored therein and incrementing said address stored therein upon receipt of said third decode output, this sequential and repetitive operation being repeated a predetermined number of times corresponding to said third command signal; and a memory array coupled to said bus means, said command decode means and said program counter means, having a plurality of multibit data words stored at memory locations therein corresponding to said address signals, for providing multibit data words as data signals to said bus means upon receipt of said address signals from said program counter means in response to either said second decode output or said third decode output from said command decode means.
Claim 3
Dependent Claim
57 words
A memory system as claimed in claim 1, wherein: said third command signal is a multiple memory location recall command signal; and said memory means produces data signals corresponding to multibit data words stored at memory locations corresponding to said address signals received from said program counter means and applies said data signals to said bus means.
Claim 4
Dependent Claim
56 words
A memory system as claimed in claim 1, wherein: said third command signal is a multiple memory location store signal; and said memory array receives data signals from said bus means and stores multibit data signals corresponding to said received data signals at memory locations corresponding to said address signals received from said program counter means.
Claim 5
Dependent Claim
53 words
A memory system as claimed in claim 1, further comprising: memory module housing means having said bus means, said command decode means, said program counter means and said memory array disposed therein, said memory module housing means having connector means connected to said bus means for removable connection to a data processing apparatus.
Claim 6
Dependent Claim
309 words
A data processing apparatus comprising: a controller means for generating command signals, address signals and data signals, said command signals comprising a load address command signal, a single memory location command signal corresponding to memory transfer operation utilizing a single memory location, and at least one multiple memory location command signal corresponding to a memory transfer operation utilizing a predetermined number of memory locations; a bidirectional bus means coupled to said controller for transmitting said command signals, address signals and data signals; a command decode means coupled to said bus means for generating respective first, second and at least a third decode output in response to receipt of said load address command signal, said single memory location command signal and said at least one multiple memory location command signal, respectively; a program counter means coupled to said bus means and to said command decode means for storing therein an address corresponding to an address signal received via said bus means upon receipt of said first decode output, for generating an address signal corresponding to said address stored therein upon receipt of said second decode output, and for sequentially and repetitively generating an address signal corresponding to said address stored therein and incrementing said address stored therein upon receipt of said third decode output, this sequential and repetitive operation being repeated a predetermined number of times corresponding to said multiple memory location command signal; and a memory array connected to said bus means, said command decode means and said program counter means having a plurality of multibit data words stored at memory locations therein corresponding to said address signals, for providing multibit data words as data signals to said bus means upon receipt of said address signals from said program counter means in response to either said second decode output or said third decode output from said command decode means.
Claim 7
Dependent Claim
309 words
A data processing apparatus comprising: a controller means for generating command signals, address signals and data signals, said command signals comprising a load address command signal, a single memory location command signal corresponding to memory transfer operation utilizing a single memory location, and at least one multiple memory location command signal corresponding to a memory transfer operation utilizing a predetermined number of memory locations; a bidirectional bus means coupled to said controller for transmitting said command signals, address signals and data signals; a command decode means coupled to said bus means for generating respective first, second and at least a third decode output in response to receipt of said load address command signal, said single memory location command signal and said at least one multiple memory location command signal, respectively; a program counter means coupled to said bus means and to said command decode means for storing therein an address corresponding to an address signal received via said bus means upon receipt of said first decode output, for generating an address signal corresponding to said address stored therein upon receipt of said second decode output, and for sequentially and repetitively generating an address signal corresponding to said address stored therein and incrementing said address stored therein upon receipt of said third decode output, this sequential and repetitive operation being repeated a predetermined number of times corresponding to said multiple memory location command signal; and a memory array connected to said bus means, said command decode means and said program counter means having a plurality of multibit data words stored at memory locations therein corresponding to said address signals, for providing multibit data words as data signals to said bus means upon receipt of said address signals from said program counter means in response to either said second decode output or said third decode output from said command decode means.
Claim 8
Dependent Claim
17 words
A data processing system according to claim 5 wherein said memory array is a read only memory.
Claim 9
Dependent Claim
16 words
A data processing system according to claim 5 wherein said memory array is a read/write memory.
Claim 10
Dependent Claim
27 words
A data processing apparatus as claimed in claim 5, wherein: said at least one multiple memory location command signal includes a multiple memory location store command signal.
Claim 11
Dependent Claim
27 words
A data processing apparatus as claimed in claim 5 wherein: said at least one multiple memory location command signal includes a multiple memory location recall command signal.
Claim 12
Dependent Claim
67 words
A data processing apparatus as claimed in claim 5 wherein: said memory means further includes a memory controller means for generating an active enable output and an inactive enable output; and said command decode means includes means connected to said memory controller means for enabling generation of decode outputs in response to received command signals only when said memory controller means is generating said active enable output.
Claim 13
Dependent Claim
79 words
A data processing apparatus as claimed in claim 5 wherein: said command signals generated by said controller means further includes an address read command signal; said command decode means includes means for generating a fourth decode output in response to said address read command signal; and said program counter means includes means for generating an address signal corresponding to said address stored therein upon receipt of said fourth decode output and applying said address signal to said bus means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-05-06 | 1988-11-05 | 1989-05-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-05-06 | 1992-11-05 | 1993-05-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-05-06 | 1996-11-05 | 1997-05-07 | $7700.00 | Window Closed / Lapsed |