Amplifier circuit for minimizing output voltage power-up transients

Claim 2

A circuit for minimizing output voltage transients in an operational amplifier resulting from powering up the operational amplifier, said operational amplifier providing an output voltage proportional to a differential between first and second input voltages coupled to a pair of differential input transistors, comprising: first current source means coupled to the pair of input transistors, for selectively providing to said differential input transistors a first bias current proportional to a bias voltage; second current source means coupled in parallel to the first current source means, for constantly providing to the differential input transistors a predetermined minimal second bias current proportional to the bias voltage; and switching means coupled to the first current source means, for selectively disabling the first current source means in response to a power control signal.

Claim 3

The circuit for minimizing output voltage transients of claim 1 wherein the first current source means comprise: a transistor having a first current electrode coupled to a first supply terminal, a control electrode coupled to the switching means, and a second current electrode coupled to the pair of differential input transistors.

Claim 4

The circuit for minimizing output voltage transients of claim 1 wherein the second current source means comprise: a transistor having a first current electrode coupled to a terminal for receiving a supply voltage, a control electrode for receiving said bias voltage, and a second current electrode coupled to the pair of differential input transistors.

Claim 5

The circuit for minimizing output voltage transients of claim 1 wherein the switching means comprise: a transistor having a control electrode coupled to a terminal for receiving the power control signal, a first current electrode coupled to a terminal for receiving a supply voltage, and a second current electrode coupled to the first current source means, for disabling the first current source means in response to the power control signal; and a CMOS transmission gate having a first terminal coupled to the first current source means, a second terminal coupled to a terminal for receiving the bias voltage, a first control input for receiving an active high form of the power control signal, and a second control input for receiving an active low form of the power control signal.

Claim 6

The circuit for minimizing output voltage transients of claim 2, further comprising: capacitance means having a first electrode coupled to the first current electrode of the transistor, and a second electrode coupled to the control electrode of the transistor, for limiting rise and fall times of voltages at the control electrode of the transistor.

Claim 7

An amplifier circuit for minimizing output voltage transients, comprising: input means for receiving an input voltage; first bias current source means for providing a first bias current to the input means; second bias current source means selectively coupled in parallel with the first bias current source means for providing a second bias current to the input means, said first bias current being substantially smaller than said second bias current; switch means for selectively disabling the second bias current source means in response to a power control signal; and output means coupled to the input means for providing an output voltage having minimized power-up voltage distortion.

Claim 8

An amplifier circuit for minimizing output voltage transients, comprising: input means for receiving an input voltage; first bias current source means for providing a first bias current to the input means; second bias current source means selectively coupled in parallel with the first bias current source means for providing a second bias current to the input means, said first bias current being substantially smaller than said second bias current; switch means for selectively disabling the second bias current source means in response to a power control signal; and output means coupled to the input means for providing an output voltage having minimized power-up voltage distortion.

Claim 9

The amplifier circuit of claim 6 wherein said first bias current source means comprise: a first transistor having a first current electrode coupled to a terminal for receiving a supply voltage, a control electrode coupled to a terminal for receiving a bias voltage, and a second current electrode coupled to the input means.

Claim 10

The amplifier circuit of claim 7 wherein said second bias current source means comprise: a second transistor having a first current electrode coupled to the terminal for receiving the supply voltage, a control electrode selectively coupled to either the supply voltage or to the bias voltage in response to the power control signal, and a second current electrode coupled to the input means.

Claim 11

The amplifier circuit of claim 8 wherein said switch means comprise: a third transistor having a first current electrode coupled to the terminal for receiving the supply voltage, a control electrode for receiving the control signal, and a second current electrode coupled to the control electrode of the first transistor; and a switch having a first terminal coupled to the control electrode of the second transistor, a second terminal coupled to the terminal for receiving the bias voltage, and a control terminal coupled to the power control signal.

Claim 12

The amplifier circuit of claim 6 wherein said first bias current source means comprise: a first resistor having a first terminal coupled to a terminal for receiving a supply voltage, and a second terminal coupled to the input means.

Claim 13

The amplifier circuit of claim 10 wherein said switch means comprise: a transistor having a first current electrode coupled to the terminal for receiving the supply voltage, a control electrode coupled to a terminal for receiving the power control signal, and a second current electrode coupled to the second bias current source means.

Claim 14

The amplifier circuit of claim 11 wherein said second bias current source means comprise: a second resistor having a first terminal coupled to the second current electrode of the transistor, and a second terminal coupled to the input means.

Claim 17

An amplifier circuit which minimizes output voltage transients, comprising: a first transistor having a first current electrode coupled to a terminal for receiving a supply voltage, a control electrode coupled to a terminal for receiving a bias voltage, and a second current electrode; a second transistor having a first current electrode coupled to the terminal for receiving the supply voltage, a control electrode, and a second current electrode coupled to the second current electrode of the first transistor; a third transistor having a first current electrode coupled to the terminal for receiving the supply voltage, a control electrode coupled to a power control signal, and a second current electrode coupled to the control electrode of the second transistor; a switch having a first terminal coupled to the control electrode of the second transistor, a second terminal coupled to the terminal for receiving the bias voltage, and a control terminal coupled to the power control signal; input means coupled to the second current electrodes of the first and second transistors, for receiving an input voltage; and output amplifier means coupled to the input means, for providing an output signal having substantially no output voltage transients in response to powering up the amplifier circuit.

Claim 18

An amplifier circuit which minimizes output voltage transients, comprising: a first transistor having a first current electrode coupled to a terminal for receiving a supply voltage, a control electrode coupled to a terminal for receiving a bias voltage, and a second current electrode; a second transistor having a first current electrode coupled to the terminal for receiving the supply voltage, a control electrode, and a second current electrode coupled to the second current electrode of the first transistor; a third transistor having a first current electrode coupled to the terminal for receiving the supply voltage, a control electrode coupled to a power control signal, and a second current electrode coupled to the control electrode of the second transistor; a switch having a first terminal coupled to the control electrode of the second transistor, a second terminal coupled to the terminal for receiving the bias voltage, and a control terminal coupled to the power control signal; input means coupled to the second current electrodes of the first and second transistors, for receiving an input voltage; and output amplifier means coupled to the input means, for providing an output signal having substantially no output voltage transients in response to powering up the amplifier circuit.

Claim 19

The amplifier circuit of claim 14 further comprising: capacitance means having a first electrode coupled to the terminal for receiving the supply voltage, and a second electrode coupled to the control electrode of the second transistor, said capacitance means limiting rise and fall times of voltages at the control electrode of the second transistor.