US4514754A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital color television signal processing circuit
Assignee: US Philips Corp
•
Filing: 1983-02-25
•
Granted: 1985-04-30
•
Expires: 2003-02-25
Abstract
Abstract In a phase control loop (3, 15, 85, 87, 89, 90) for the A/D converter of a digital color television signal processing circuit an input (13) and an output (23) of a delay circuit (21) are connected to a comparator (19) to derive a control signal from the inequality of the signals at said input and output.
Inventors
- 👤 Antonius H. H. J. Nillesen
- 👤 Petrus W. G. Welles
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 23:29
CPC Classifications
H; H04; H04N; H04N9/00; H04N9/44; H04N9/455
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
167 words
A digital colour television signal processing circuit comprising an analogue-to-digital converter which is controlled by a pulse generator producing a pulse signal of four times the chrominance subcarrier frequency, a comparison circuit being coupled to the output of the analogue-to-digital converter for comparing different digital burst samples and for obtaining therefrom a control signal for a phase control loop of the pulse generator, characterised in that the burst samples to be compared are obtained from an input (17) and an output (23) of a delay circuit having such a delay that at a correct pulse generator phase the difference between the burst samples at the input (17) and at the output (23) thereof becomes zero, while the comparison circuit is an inequality detection circuit (15) for detecting independently of the amplitude value of the burst samples inequality of the amplitude value of the burst samples at the input and the output of the delay circuit and converting that inequality, if present, into a control signal (at 91).
Claim 2
Dependent Claim
167 words
A digital colour television signal processing circuit comprising an analogue-to-digital converter which is controlled by a pulse generator producing a pulse signal of four times the chrominance subcarrier frequency, a comparison circuit being coupled to the output of the analogue-to-digital converter for comparing different digital burst samples and for obtaining therefrom a control signal for a phase control loop of the pulse generator, characterised in that the burst samples to be compared are obtained from an input (17) and an output (23) of a delay circuit having such a delay that at a correct pulse generator phase the difference between the burst samples at the input (17) and at the output (23) thereof becomes zero, while the comparison circuit is an inequality detection circuit (15) for detecting independently of the amplitude value of the burst samples inequality of the amplitude value of the burst samples at the input and the output of the delay circuit and converting that inequality, if present, into a control signal (at 91).
Claim 3
Dependent Claim
84 words
A digital colour television signal processing circuit as claimed in claim 1, characterized in that coupled to an output (27) of the inequality detection circuit there is a state detection circuit (71) by means of which it can be detected whether the state control loop is in the pulled-in or the non-pulled-in state and in response to an output signal (at 107) a changeover (113) of a time constant (85, 87, 89, 90) can be obtained in the phase control loop (3, 15, 9).
Claim 4
Dependent Claim
27 words
A digital colour television signal processing circuit as claimed in claim 2, characterized in that the state detection circuit (71) has a colour killing signal output (109).
Claim 5
Dependent Claim
96 words
A digital colour television signal processing circuit as claimed in claim 1 or 2, for processing a PAL-colour television signal, characterized in that an input (101) of the state detection circuit (71) is coupled via a comparison circuit (97, 99) for comparing output signals of the inequality detection circuit (15) occurring in two consecutive horizontal scanning periods at an output (55) of the inequality detection circuit (15) while the state detection circuit (71) comprises a circuit (263, 269) for establishing a correct switching state of a change-over signal generator (208) at half the horizontal scanning frequency.
Claim 6
Dependent Claim
43 words
A digital colour television signal processing circuit as claimed in claim 4 for a PAL-colour television signal, characterized in that the delay circuit (21) produces a delay of an odd number of times the period of four times the chrominance subcarrier frequency (4f).
Claim 7
Dependent Claim
50 words
A digital colour television signal processing circuit as claimed in any of the claims 1 to 3, inclusive for a NTSC colour television signal, characterized in that the delay circuit (21) produces a delay of an even number of times the period of four times the chrominance subcarrier frequency (4f).
References Cited (Backward Citations)
US4122487A
Cited
US4291332A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-04-29 | 1988-10-29 | 1989-04-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-04-29 | 1992-10-29 | 1993-04-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-04-29 | 1996-10-29 | 1997-04-30 | $7700.00 | Window Closed / Lapsed |