Process for making stacked high voltage rectifiers

Claim 2

In a process for making stacked high voltage rectifiers, the improvement comprising: coating each of a plurality of silicon wafers with paint-on P-type and N-type dopants respectively on opposite sides of each wafer, said coating being carried out by: slowly rotating the wafer at a speed of less than about twenty revolutions per minute while said wafer is supported at its edge, in a horizontal plane, by a set of radially widely spaced support fingers, applying one of said dopants with an applicator that is gradually moved from the center to the outer edge of one side of said wafer while said wafer is being slowly rotated, repeating said slowly rotating and applying steps with the wafer inverted, for applying the other of said dopants to the opposite side of said wafer, said slow rotation limiting spin-off and runover of each dopant onto the reverse side of said wafer, and thereafter tightly coin stacking a plurality of wafers, each coated in accordance with the preceding steps, with similary doped sides facing each other, and diffusing said wafers by heating said tightly coin stacked wafers in a diffusion furnace.

Claim 3

In a process for making stacked high voltage rectifiers, the improvement for alloying together a stack of semiconductor wafers each doped on opposite sides with respective opposite conductivity dopants, comprising: providing a metal layer on at least one side of each doped wafer, coin stacking a plurality of said metal layer provided wafers with doped sides of opposite conductivity facing each other, there being at least one metal layer between each pair of wafers, mounting said stacked wafers in a compression jig, said jig exerting a compressive force on said stack of wafers, heating said stacked wafers while in said compression jig to a temperature sufficient to cause wetting of the metal while maintaining compression of said stack with said jig, and quickly discontinuing said heating and reducing the compressive force on said stacked wafers when said wetting temperature has been reached, and wherein said heating is carried out in a rolling furnace, the furnace being rolled into heating engagement with said stacked wafers to initiate heating while said stacked wafers are in said compression jig, said furnace being quickly rolled away from said stacked wafers and compression jig once said wetting temperature has been reached.

Claim 4

In a process for making stacked high voltage rectifiers, the improvement for alloying together a stack of semiconductor wafers each doped on opposite sides with respective opposite conductivity dopants, comprising: providing a metal layer on at least one side of each doped wafer, coin stacking a plurality of said metal layer provided wafers with doped sides of opposite conductivity facing each other, there being at least one metal layer between each pair of wafers, mounting said stacked wafers in a compression jig, said jig exerting a compressive force on said stack of wafers, heating said stacked wafers while in said compression jig to a temperature sufficient to cause wetting of the metal while maintaining compression of said stack with said jig, and quickly discontinuing said heating and reducing the compressive force on said stacked wafers when said wetting temperature has been reached, and wherein said heating is carried out in a rolling furnace, the furnace being rolled into heating engagement with said stacked wafers to initiate heating while said stacked wafers are in said compression jig, said furnace being quickly rolled away from said stacked wafers and compression jig once said wetting temperature has been reached.

Claim 5

A process according to claim 2 wherein said heating is carried out in a vacuum or in an inert atmosphere.

Claim 6

A process according to claim 2 wherein said semiconductor is silicon, wherein said metal layer is vapor deposited silver, and wherein said heating is to a wetting temperature that is above the silicon-silver eutectic temperature.

Claim 7

A process according to claim 2 wherein said compression is maintained substantially constant by said jig throughout said heating.

Claim 8

A process for making stacked high voltage rectifiers, comprising the steps of: coating each of a plurality of silicon wafers with paint-on P-type and N-type dopants respectively on opposite sides of each wafer, said coating being carried out on each side of said wafer by applying the respective dopant with an applicator that is gradually moved from the center to the outer edge of said wafer side while said wafer is horizontally, peripherally supported by spaced support fingers and slowly rotated at a speed of less than about twenty revolutions per minute, diffusing said wafers by heating in a diffusion furnace a tightly coin stacked plurality of wafers, each coated in accordance with the preceding step and arranged with similarly doped sides facing each other, separating said diffused wafers and evaluating the reverse recovery time thereof, coating the N-type doped side of each wafer with a paint-on noble metal dopant applied with an applicator that is gradually moved from the center to the outer edge of said N-type doped side of said wafer while said wafer is slowly rotated at a speed of less than about twenty revolutions per minute, diffusing and driving in said noble metal in a diffusion furnace at a temperature adjusted in accordance with the measured and desired reverse recovery times of said wafer, vapor depositing silver on both sides of each wafer, heating a coin stacked plurality of said silver coated wafers in a vacuum or inert atmosphere furnace while maintaining said wafer stack under a compressive force exerted by a compression jig, said stack being heated to a temperature, above the silicon-silver eutectic temperature, at which the silver wets and flows smoothly, and thereafter quickly discontinuing said heating, said compressive force being programmatically varied in accordance with the temperature of said stack, forming individual stacked junction dice from said wafer stack, attaching leads to each die, etching each die and attached leads to remove edge damage thereof, and encapsulating the resultant product to form said stacked high voltage rectifier.

Claim 9

A process for making stacked high voltage rectifiers, comprising the steps of: coating each of a plurality of silicon wafers with paint-on P-type and N-type dopants respectively on opposite sides of each wafer, said coating being carried out on each side of said wafer by applying the respective dopant with an applicator that is gradually moved from the center to the outer edge of said wafer side while said wafer is horizontally, peripherally supported by spaced support fingers and slowly rotated at a speed of less than about twenty revolutions per minute, diffusing said wafers by heating in a diffusion furnace a tightly coin stacked plurality of wafers, each coated in accordance with the preceding step and arranged with similarly doped sides facing each other, separating said diffused wafers and evaluating the reverse recovery time thereof, coating the N-type doped side of each wafer with a paint-on noble metal dopant applied with an applicator that is gradually moved from the center to the outer edge of said N-type doped side of said wafer while said wafer is slowly rotated at a speed of less than about twenty revolutions per minute, diffusing and driving in said noble metal in a diffusion furnace at a temperature adjusted in accordance with the measured and desired reverse recovery times of said wafer, vapor depositing silver on both sides of each wafer, heating a coin stacked plurality of said silver coated wafers in a vacuum or inert atmosphere furnace while maintaining said wafer stack under a compressive force exerted by a compression jig, said stack being heated to a temperature, above the silicon-silver eutectic temperature, at which the silver wets and flows smoothly, and thereafter quickly discontinuing said heating, said compressive force being programmatically varied in accordance with the temperature of said stack, forming individual stacked junction dice from said wafer stack, attaching leads to each die, etching each die and attached leads to remove edge damage thereof, and encapsulating the resultant product to form said stacked high voltage rectifier.