US4508000A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Frequency-selectable signal generator
Assignee: Citizen Watch Co Ltd
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Filing: 1983-04-21
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Granted: 1985-04-02
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Expires: 2003-04-21
Abstract
Abstract Disclosed is a frequency-selectable signal generator in which a numeric datum is parallel-transferred to a full adder circuit repeatedly under the control of clock pulse signals, thereby outputting an overflow signal, which is a precise division of accumulation of repeatedly inputting numbers. The frequency of the overflow signal varies with the number represented by the numeric datum. The output signal has a regular pulse-to-pulse interval, and therefore it can be used in producing a musical note.
Inventors
- 👤 Fuminori Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 07:31
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/60; G06F7/68; G06F7/38; G06F7/48; G06F7/50; G10; G10H; G10H5/00; G10H5/02; G10H5/06; Y; Y10; Y10S; Y10S84/00; Y10S84/11; Y10S84/23
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
195 words
A frequency-selectable signal generator comprising: reference signal generator means for generating clock signals; frequency instructing means for supplying parallel numeric datum pertaining to a given frequency to be generated; and accumulator means having first input terminal means for receiving said parallel numeric datum and second input terminal means for receiving the clock signals from said reference signal generator means, which are used to enable the accumulator means to accumulate said parallel numeric datum, said accumulator means including a binary counter composed of a series alternation of flip-flops and exclusive OR gates, and a drive circuit connected to said exclusive OR gates via bus conductors, thus enabling said drive circuit to drive said binary counter via said bus conductors synchronously with said clock signals, whereby when said parallel numeric datum is supplied to said first input terminal means of said accumulator means and when said clock signals are supplied to said second input terminal means of said accumulator means, said accumulator means performing addition of the number represented by said parallel numeric datum for every one clock pulse, thus outputting an overflow signal whose frequency is proportional to the number represented by said parallel numeric datum.
Claim 2
Dependent Claim
195 words
A frequency-selectable signal generator comprising: reference signal generator means for generating clock signals; frequency instructing means for supplying parallel numeric datum pertaining to a given frequency to be generated; and accumulator means having first input terminal means for receiving said parallel numeric datum and second input terminal means for receiving the clock signals from said reference signal generator means, which are used to enable the accumulator means to accumulate said parallel numeric datum, said accumulator means including a binary counter composed of a series alternation of flip-flops and exclusive OR gates, and a drive circuit connected to said exclusive OR gates via bus conductors, thus enabling said drive circuit to drive said binary counter via said bus conductors synchronously with said clock signals, whereby when said parallel numeric datum is supplied to said first input terminal means of said accumulator means and when said clock signals are supplied to said second input terminal means of said accumulator means, said accumulator means performing addition of the number represented by said parallel numeric datum for every one clock pulse, thus outputting an overflow signal whose frequency is proportional to the number represented by said parallel numeric datum.
Claim 3
Dependent Claim
27 words
A frequency-selectable signal generator according to claim 1 wherein it further comprises a frequency divider for dividing the frequency of the overflow signal from said accumulator means.
Claim 4
Dependent Claim
65 words
A frequency-selectable signal generator according to claim 1 wherein said accumulator means is of the type in which the accumulation result is stored as an augend on which the next addition is performed; a series of additions are repeated synchronous by with said clock signals; and when the overflow signal appears, the remainder is stored as an augend on which the subsequent addition is performed.
Claim 5
Dependent Claim
146 words
A musical note generating apparatus comprising: reference signal generator means for generating clock signals; musical note instructing means for supplying parallel numeric data pertaining to different frequencies corresponding to musical notes; accumulator means responsive to each clock pulse from said referene signal generator for adding the number represented by said parallel numeric datum to the previous accumulation result and for outputting an overflow signal as a musical note signal, said accumulator means including a binary counter composed of a series alternation of flip-flops and exclusive OR gates, and a drive circuit connected to said exclusive OR gates via bus conductors, thus enabling said drive circuit to drive said binary counter via said bus conductors synchronously with said clock signals; a frequency divider for dividing the frequency of the overflow signal; and an electro-to-audio converter for converting the frequency-divided musical note signal to an audio output signal.
Claim 6
Dependent Claim
146 words
A musical note generating apparatus comprising: reference signal generator means for generating clock signals; musical note instructing means for supplying parallel numeric data pertaining to different frequencies corresponding to musical notes; accumulator means responsive to each clock pulse from said referene signal generator for adding the number represented by said parallel numeric datum to the previous accumulation result and for outputting an overflow signal as a musical note signal, said accumulator means including a binary counter composed of a series alternation of flip-flops and exclusive OR gates, and a drive circuit connected to said exclusive OR gates via bus conductors, thus enabling said drive circuit to drive said binary counter via said bus conductors synchronously with said clock signals; a frequency divider for dividing the frequency of the overflow signal; and an electro-to-audio converter for converting the frequency-divided musical note signal to an audio output signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-04-01 | 1988-10-01 | 1989-04-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-04-01 | 1992-10-01 | 1993-04-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-04-01 | 1996-10-01 | 1997-04-02 | $7700.00 | Window Closed / Lapsed |