Control apparatus for rotation type storage device

Claim 2

A control apparatus for a rotation type storage device which is divided into a plurality of regions each of which has an address area, serving for recording control information concerning addresses and an indication of the leading part of the region, and a data area serving for recording data, comprising: (a) memory means for storing control information which includes addresses and indication of the leading part of a region to be accessed; (b) register means for storing temporarily therein control information read from said address area in a region; (c) comparison means for comparing said control information read out from said memory means with said control information from said register means; and (d) control means for controlling said data area to be accessed in accordance with the result of comparison effected by said comparison means.

Claim 3

A control apparatus according to claim 1, wherein a control bit which serves for comparing said first and second control information is stored in said memory means, and said comparison means compares said control information read out from said memory means in accordance with an indication of said control bit.

Claim 4

A control apparatus according to claim 1, further including counter means for counting a shift pulse which serves for shifting said first control information in said register means, wherein said comparison means compares said first and second control information when said counter counts to a predetermined value.

Claim 5

A control apparatus according to claim 1, further including bus means for transmitting said control information and said data which are read and written from/to the storage device, and switching means for switching said bus means to said register means in accordance with the indentification of said indication of the leading information by said comparison means.

Claim 6

A control apparatus according to claim 1, further including a control circuit for inhibiting comparing in accordance with non-identifying of the comparison by said comparison means.

Claim 7

A control apparatus for a rotation type storage device which is divided into a plurality of sectors each of which includes an address area serving for recording the first information of the address assigned thereto, and a data area serving for recording data, comprising: (a) a bus connected to a host system and transferring at least read/write commands and second control information including addresses and an indication of the leading part of a sector to read and to be written from/into said data area of said sector; (b) bus interface control means for analyzing the command transferred by said bus; (c) memory means for storing said second control information in accordance with the result of the analysis of the command by said bus interface control means;

Claim 8

A control apparatus for a rotation type storage device which is divided into a plurality of sectors each of which includes an address area serving for recording the first information of the address assigned thereto, and a data area serving for recording data, comprising: (a) a bus connected to a host system and transferring at least read/write commands and second control information including addresses and an indication of the leading part of a sector to read and to be written from/into said data area of said sector; (b) bus interface control means for analyzing the command transferred by said bus; (c) memory means for storing said second control information in accordance with the result of the analysis of the command by said bus interface control means;

Claim 9

(d) means including a shift register for storing temporarily therein said first information read from said address area; (e) comparison means for comparing said first information read out from said shift register with said second control information read out from said memory means; (f) an internal bus for transferring at least said second control information and said data read from and written into said data area; and (g) selecting means for selecting said second control information read out from said memory means or the data from said internal bus in accordance with the result of the comparison effected by said comparison means.

Claim 10

(d) means including a shift register for storing temporarily therein said first information read from said address area; (e) comparison means for comparing said first information read out from said shift register with said second control information read out from said memory means; (f) an internal bus for transferring at least said second control information and said data read from and written into said data area; and (g) selecting means for selecting said second control information read out from said memory means or the data from said internal bus in accordance with the result of the comparison effected by said comparison means.

Claim 11

A control apparatus according to claim 1, wherein said memory means stores a control bit to indicate wherther or not said second control information is to be compared, and said comparison means compares the relevant second control information with reference to said control bit.

Claim 12

A control apparatus according to claim 6, further including a counter to count in synchronism with a shift pulse to shift information within said shift register, comparison being made by said comparison means each time said counter counts a predetermined value.

Claim 13

A control apparatus according to claim 6, wherein said indication of the leading part of a sector is previously stored in said memory means.

Claim 14

A control apparatus according to claim 6, wherein, when said indication of the leading part of a sector is identified by said comparison means, said selecting means selects said internal bus and data transfer is made between said shift register and said internal bus.

Claim 15

A control apparatus according to claim 6, wherein, when said first information and said second control information are not identical as a result of comparison by said comparison means, said bus interface control means functions to interrupt the subsequent comparing operation.

Claim 16

A control apparatus according to claim 6, further including a device interface circuit with which a storage device with any recording format is coupled, the second control information inherent to a recording format being transferred from said host system to be stored in said memory means.

Claim 17

A control circuit for a magnetic recording device which includes a plurality of sectors each of which has a data area serving for recording data, and an address area serving for recording the first control information including addresses to define a recording format of the sector and indication of the leading part of said data area and said address area, wherein the data read from or written into a data area within said device is transferred to or from a host system via an internal bus, comprising: (a) memory means for storing second control information which includes addresses to define a recording format of the sector to be accessed and indication of the leading part of said data area and said address area to be accessed, and for storing a control bit to determine whether said second control information should be compared; (b) an address register for designating the address of said memory in order for said second control information and said control bit to be read out of said memory or to be written therein; (c) converting means for serial/parallel conversion of said data or said second control information transferred via said internal bus to be written into a sector of said magnetic recording device, and for parallel/serial conversion of said data or said first control information read out of a sector of said magnetic recording device; (d) comparator means for comparing said second control information outputted from said memory with said first control information transferred from said converting means when said control bit outputted from said memory means indicates the comparisong to be required; (e) selecting means for transferring the data from said internal bus to said converting means or from said converting means to said internal bus in accordance with the coincidence of the indication included in said first and said second control information compared by said comparator means; the address in said address register being readdressed to output, from said memory means, said second control information which is compared successively with said first control information by said comparator means, resulting in that the subsequent comparison is interrupted if said first and said second control informations are not coincident.

Claim 18

A control circuit for a magnetic recording device which includes a plurality of sectors each of which has a data area serving for recording data, and an address area serving for recording the first control information including addresses to define a recording format of the sector and indication of the leading part of said data area and said address area, wherein the data read from or written into a data area within said device is transferred to or from a host system via an internal bus, comprising: (a) memory means for storing second control information which includes addresses to define a recording format of the sector to be accessed and indication of the leading part of said data area and said address area to be accessed, and for storing a control bit to determine whether said second control information should be compared; (b) an address register for designating the address of said memory in order for said second control information and said control bit to be read out of said memory or to be written therein; (c) converting means for serial/parallel conversion of said data or said second control information transferred via said internal bus to be written into a sector of said magnetic recording device, and for parallel/serial conversion of said data or said first control information read out of a sector of said magnetic recording device; (d) comparator means for comparing said second control information outputted from said memory with said first control information transferred from said converting means when said control bit outputted from said memory means indicates the comparisong to be required; (e) selecting means for transferring the data from said internal bus to said converting means or from said converting means to said internal bus in accordance with the coincidence of the indication included in said first and said second control information compared by said comparator means; the address in said address register being readdressed to output, from said memory means, said second control information which is compared successively with said first control information by said comparator means, resulting in that the subsequent comparison is interrupted if said first and said second control informations are not coincident.