US4504929A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1982-11-24
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Granted: 1985-03-12
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Expires: 2002-11-24
Abstract
Abstract A dynamic semiconductor memory device provides a selected real cell, which is connected to a first of a pair of bit lines connected to a sense amplifier, and a dummy cell which is connected to a second of the pair of bit lines so as to perform a read-out operation. The dynamic semiconductor memory cell further provides an active restore circuit for pulling up the bit line potential of the bit line on the higher potential side of the pair of bit lines, in which the potential difference is increased by the read-out operation. The dynamic semiconductor cell can also provide a write-in circuit for charging the selected real cell through the bit line. A test power source pad is provided in the active restore circuit or the write in circuit so that when the reference level of the real cell is tested an optional power source can be applied from the test power source pad instead of from a normal power source.
Inventors
- 👤 Yoshihiro Takemae
- 👤 Tsuyoshi Ohira
- 👤 Seiji Enomoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 03:19
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/02; G11C29/026; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4091; G11C29/04; G11C29/50; G11C2029/5004
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
139 words
A dynamic semiconductor memory device comprising: a pair of bit lines including first and second bit lines; a sense amplifier operatively connected to said pair of bit lines; a real cell operatively connected to said first bit line of said pair of bit lines; a dummy cell, operatively connected to said second bit line of said pair of bit lines, for performing a read-out operation; an active restore circuit, operatively connected to said pair of bit lines, for pulling up the bit line potential of the bit line on the higher potential side of said pair of bit lines, in which the potential difference is increased by the read-out operation; and a test power source pad, operatively connected to said active restore circuit, for receiving and providing an optional and normal power source voltage to said active restore circuit.
Claim 2
Dependent Claim
139 words
A dynamic semiconductor memory device comprising: a pair of bit lines including first and second bit lines; a sense amplifier operatively connected to said pair of bit lines; a real cell operatively connected to said first bit line of said pair of bit lines; a dummy cell, operatively connected to said second bit line of said pair of bit lines, for performing a read-out operation; an active restore circuit, operatively connected to said pair of bit lines, for pulling up the bit line potential of the bit line on the higher potential side of said pair of bit lines, in which the potential difference is increased by the read-out operation; and a test power source pad, operatively connected to said active restore circuit, for receiving and providing an optional and normal power source voltage to said active restore circuit.
Claim 3
Dependent Claim
60 words
A dynamic semiconductor memory device according to claim 1, wherein, when said dynamic semiconductor memory device is tested a voltage lower than the normal power source is supplied to said test power source pad, and the read-out operation in said real cell is repeated while decreasing the voltage so as to determine the minimum voltage level of said real cell.
Claim 4
Dependent Claim
76 words
A dynamic semiconductor memory device comprising: first and second bit lines; a sense amplifier operatively connected to said first and second bit lines; a real cell operatively connected to said second bit line; a write-in circuit, operatively connected to said real cell, for charging the real cell; and a test power source pad having an optional power source voltage, operatively connected to said write-in circuit, for applying the optional power source voltage to said write-in circuit.
Claim 5
Dependent Claim
76 words
A dynamic semiconductor memory device comprising: first and second bit lines; a sense amplifier operatively connected to said first and second bit lines; a real cell operatively connected to said second bit line; a write-in circuit, operatively connected to said real cell, for charging the real cell; and a test power source pad having an optional power source voltage, operatively connected to said write-in circuit, for applying the optional power source voltage to said write-in circuit.
Claim 6
Dependent Claim
26 words
A dynamic semiconductor memory device according to claim 3, further comprising a data-in buffer operatively connected between said test power source pad and said write-in circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-03-11 | 1988-09-10 | 1989-03-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-03-11 | 1992-09-10 | 1993-03-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-03-11 | 1996-09-10 | 1997-03-12 | $7700.00 | Window Closed / Lapsed |