US4503523A
Expired / Lapsed
US
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Dynamic reference potential generating circuit arrangement
Assignee: International Business Machines Corp
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Filing: 1982-06-30
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Granted: 1985-03-05
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Expires: 2002-06-30
Abstract
Abstract This dynamic reference potential generating circuit arrangement is especially adaptable to a binary data storage array of the type wherein each data storage cell comprises a single transistor and a single capacitor. A reference potential generating circuit for such an array comprises a pair of such identical transistors connected in parallel and a pair of identical capacitors, connected in common to the transistor emitter electrodes which capacitors couple the emitters to a digit line and to a refresh line, respectively. This arrangement develops a potential swing at the emitter electrodes equal to half of the potential swing that would develop at the emitter electrode of the transistor of a single data storage cell for the same signal swing on the digit line. Basically, the total capacitance connected to the emitter electrode of the generator circuit transistors is twice the capacitance connected to the emitter electrode of the transistor of a single storage cell. Therefore, the potential applied through the capacitor to the emitter electrode is exactly half of that applied through the capacitor connected to the storage cell transistor emitter electrode.
Inventors
- 👤 Joseph R. Cavaliere
- 👤 Peter T. Liu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 00:39
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/4067; G11C11/407; G11C11/409; G11C11/4099
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
139 words
A dynamic reference potential generating circuit arrangement particularly for use in an electronic binary data storge array of the type having a multiple of cells, each comprising a transistor and a capacitor connected to word and digit lines to which differential sensing circuitry is attached, said arrangement comprising, a reference line, a refresh line, a point of fixed reference potential, a pair of said transistors each having emitter, base and collector electrodes, circuitry interconnecting said emitter electrodes, circuitry connecting said base electrodes to said reference line, circuitry connecting said collector electrodes to said point of fixed reference potential, a pair of capacitors having given electrodes connected in common to said emitter electrodes and having one of said other electrodes connected to one of said digit lines, and circuitry connecting the other of said other electrodes to said refresh line.
Claim 2
Dependent Claim
139 words
A dynamic reference potential generating circuit arrangement particularly for use in an electronic binary data storge array of the type having a multiple of cells, each comprising a transistor and a capacitor connected to word and digit lines to which differential sensing circuitry is attached, said arrangement comprising, a reference line, a refresh line, a point of fixed reference potential, a pair of said transistors each having emitter, base and collector electrodes, circuitry interconnecting said emitter electrodes, circuitry connecting said base electrodes to said reference line, circuitry connecting said collector electrodes to said point of fixed reference potential, a pair of capacitors having given electrodes connected in common to said emitter electrodes and having one of said other electrodes connected to one of said digit lines, and circuitry connecting the other of said other electrodes to said refresh line.
Claim 3
Dependent Claim
211 words
An electronic binary data storage array comprising a multiple of word lines, a multiple of digit lines, at least one reference line, at least one refresh line, a multiple of storage capacitors, and a multiple of transistors each having an emitter electrode, a base electrode and a collector electrode, a binary data storage section comprising a multiple of cells, each cell comprising a single one of said capacitors and a single one of said transistors with the emitter-collector circuit and the capacitor connected in series between a digit line and a point of fixed reference potential and with the base electrode connected to a word line, a storage cell sensing section comprising electronic circuitry having a pair of differential input terminals and having an output terminal with one of said input terminals coupled to a digit line and the other input terminal available for dynamic reference potential, and reference potential generating section comprising two of said capacitors connected in series between said refresh line and said other input terminal of said electronic sensing circuitry, and two of said transistors connected in parallel between the junction point between said series connected capacitors and said point of fixed reference potential, the bases of said two transistors being commonly connected to said reference line.
Claim 4
Dependent Claim
211 words
An electronic binary data storage array comprising a multiple of word lines, a multiple of digit lines, at least one reference line, at least one refresh line, a multiple of storage capacitors, and a multiple of transistors each having an emitter electrode, a base electrode and a collector electrode, a binary data storage section comprising a multiple of cells, each cell comprising a single one of said capacitors and a single one of said transistors with the emitter-collector circuit and the capacitor connected in series between a digit line and a point of fixed reference potential and with the base electrode connected to a word line, a storage cell sensing section comprising electronic circuitry having a pair of differential input terminals and having an output terminal with one of said input terminals coupled to a digit line and the other input terminal available for dynamic reference potential, and reference potential generating section comprising two of said capacitors connected in series between said refresh line and said other input terminal of said electronic sensing circuitry, and two of said transistors connected in parallel between the junction point between said series connected capacitors and said point of fixed reference potential, the bases of said two transistors being commonly connected to said reference line.
Claim 5
Dependent Claim
107 words
A dynamic reference potential generating circuit arrangement for connection to a sensing circuit via a bit line, to a refresh line, to a reference line and to a source of potential, said circuit arrangement comprising a pair of bipolar transistors each having a base, a collector and an emitter electrode, said emitter electrodes being connected together, said collector electrodes being connected together to said source of potential, said base electrodes being connected together to said reference line, a pair of capacitors, one of said capacitors connecting said emitter electrodes to said bit line and the other of said capacitors connecting said emitter electrodes to said refresh line.
Claim 6
Dependent Claim
107 words
A dynamic reference potential generating circuit arrangement for connection to a sensing circuit via a bit line, to a refresh line, to a reference line and to a source of potential, said circuit arrangement comprising a pair of bipolar transistors each having a base, a collector and an emitter electrode, said emitter electrodes being connected together, said collector electrodes being connected together to said source of potential, said base electrodes being connected together to said reference line, a pair of capacitors, one of said capacitors connecting said emitter electrodes to said bit line and the other of said capacitors connecting said emitter electrodes to said refresh line.
Claim 7
Dependent Claim
22 words
A dynamic reference potential generating circuit as defined in claim 3 and wherein said sensing circuit is a differential amplifying circuit arrangement.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-03-04 | 1988-09-03 | 1989-03-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-03-04 | 1992-09-03 | 1993-03-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-03-04 | 1996-09-03 | 1997-03-05 | $7700.00 | Window Closed / Lapsed |