Full-bridge electronic inverter circuit

Claim 2

An inverter circuit adapted to be powered from a source of DC voltage and operative to provide an AC output for a load, said source of DC voltage having a B+ terminal and a B- terminal, said circuit comprising: a first pair of transistor switching means connected in series with one another at a first junction to form a first series-pair, each of said transistor switching means having a pair of switching control terminals, said first series-pair being connected between said B+ terminal and said B- terminal; a second pair of transistor switching means connected in series with one another at a second junction to form a second series-pair, each of said transistor switching means having a pair of switching control terminals, said second series-pair being connected between said B+ terminal and said B- terminal; positive feedback drive means connected in circuit between said junctions and said pairs of switching control terminals, said drive means being operative to drive said series-pairs in alternating push-pull fashion such as to provide between said junctions an output voltage characterized by alternating back and forth between a substantially constant-magnitude positive voltage and a substantially constant-magnitude negative voltage, but with a distinct period between each alternation where the output voltage is substantially of zero magnitude; and electrical connection means connected in circuit with said junctions and operative to provide said AC output for said load.

Claim 3

The inverter circuit of claim 1 wherein an inductance means is connected in circuit with said junctions.

Claim 4

The inverter circuit of claim 1 wherein said drive means comprises a first and a second saturable inductor means, said saturable inductor means being operative to determine the length of said distinct period.

Claim 5

The inverter circuit of claim 3 wherein said first saturable inductor means has a saturation period that is distinctly longer than that of said second inductor means.

Claim 6

The inverter circuit of claim 1 and rectifier means connected in circuit with each transistor means.

Claim 7

An inverter circuit adapted to be powered from a source of DC voltage and operative to provide an AC output voltage for a load, said source of DC voltage having a B+ terminal and a B- terminal, said circuit comprising: a first pair of transistor switching means connected in series with one another at a first junction to form a first series-pair, each of said transistor switching means having a pair of switching control terminals, said first series-pair being connected between said B+ terminal and said B- terminal; a second pair of transistor switching means connected in series with one another at a second junction to form a second series-pair, each of said transistor switching means having a pair of switching control terminals, said second series-pair being connected between said B+ terminal and said B- terminal; positive feedback drive means connected in circuit between said junctions and said pairs of switching control terminals, and operative to drive said series-pairs in alternating push-pull fashion such as to provide between said junctions an output voltage cyclically passing through four distinct time periods: (i) a first period during which the output voltage is of substantially constant positive magnitude, (ii) a second period during which the output voltage is of substantially zero magnitude, (iii) a third period during which the output voltage is of substantially constant negative magnitude, and (iv) a fourth period during which the output voltage is of substantially zero magnitude; and electrical connection means connected in circuit with said junctions and operative to provide said AC output voltage for said load.

Claim 8

An inverter circuit adapted to be powered from a source of DC voltage and operative to provide an AC output voltage for a load, said source of DC voltage having a B+ terminal and a B- terminal, said circuit comprising: a first pair of transistor switching means connected in series with one another at a first junction to form a first series-pair, each of said transistor switching means having a pair of switching control terminals, said first series-pair being connected between said B+ terminal and said B- terminal; a second pair of transistor switching means connected in series with one another at a second junction to form a second series-pair, each of said transistor switching means having a pair of switching control terminals, said second series-pair being connected between said B+ terminal and said B- terminal; positive feedback drive means connected in circuit between said junctions and said pairs of switching control terminals, and operative to drive said series-pairs in alternating push-pull fashion such as to provide between said junctions an output voltage cyclically passing through four distinct time periods: (i) a first period during which the output voltage is of substantially constant positive magnitude, (ii) a second period during which the output voltage is of substantially zero magnitude, (iii) a third period during which the output voltage is of substantially constant negative magnitude, and (iv) a fourth period during which the output voltage is of substantially zero magnitude; and electrical connection means connected in circuit with said junctions and operative to provide said AC output voltage for said load.

Claim 9

The inverter circuit of claim 6 wherein said first and third periods are substantially of equal durations, and where said second and fourth periods are also substantially of equal durations.

Claim 10

The inverter circuit of claim 7 wherein said second and fourth periods each is of about half the duration as that of each of said first and third periods.

Claim 11

The inverter circuit of claim 6 wherein said drive means comprises a first and a second saturable inductor means, which inductor means are non-coupled to each other.

Claim 12

The inverter circuit of claim 9 wherein said first inductor means saturates more readily than said second inductor means.

Claim 13

A self-oscillating inverter circuit adapted to be powered from a source of DC voltage and operative to provide an AC output voltage for a load, said source of DC voltage providing its output between an X-terminal and a Y-terminal, said circuit comprising: I. four transistors, Qax, Qay, Qbx and Qby, each having an emitter, a collector and a base, said four transistors being connected between said X-terminal and said Y-terminal in such a way that: (i) transistors Qax and Qbx are connected with their collectors to said X-terminal, (ii) transistors Qay and Qby are connected with their emitters to said Y-terminal, (iii) transistor Qax is connected with its emitter to an output connection point Qa, to which the collector of transistor Qay is also connected, and (iv) transistor Qbx is connected with its emitter to an output connection point Qb, to which the collector of transistor Qby is also connected; II. output connection means operative to permit connection of said load in circuit between said output connection points, Qa and Qb; and III. positive feedback means connected in circuit between the bases of said four transistors and said output connection points Qa and Qb, said feedback means operative to provide current drive to the bases of said four transistors in cyclic alternation between transistors Qax and Qby, and transistors Qay and Qbx, whereby transistors Qax and Qby are rendered conductive in alternating fashion with transistors Qdx and Qay, the length of the period during which transistor Qax is rendered conductive being distinctly different from that during which Qby is rendered conductive, and the length of the period during which transistor Qbx is rendered conductive being distinctly different from that during which Qay is rendered conductive; whereby said AC output voltage, which is provided between connection points Qa and Qb, may be characterized by four cyclically re-occurring time periods: (i) a first period of a substantially constant-magnitude positive voltage, (ii) a second period of substantially zero-magnitude voltage, (iii) a third period of a substantially constant-magnitude negative voltage, and (iv) a fourth period of substantially zero-magnitude voltage.

Claim 14

A self-oscillating inverter circuit adapted to be powered from a source of DC voltage and operative to provide an AC output voltage for a load, said source of DC voltage providing its output between an X-terminal and a Y-terminal, said circuit comprising: I. four transistors, Qax, Qay, Qbx and Qby, each having an emitter, a collector and a base, said four transistors being connected between said X-terminal and said Y-terminal in such a way that: (i) transistors Qax and Qbx are connected with their collectors to said X-terminal, (ii) transistors Qay and Qby are connected with their emitters to said Y-terminal, (iii) transistor Qax is connected with its emitter to an output connection point Qa, to which the collector of transistor Qay is also connected, and (iv) transistor Qbx is connected with its emitter to an output connection point Qb, to which the collector of transistor Qby is also connected; II. output connection means operative to permit connection of said load in circuit between said output connection points, Qa and Qb; and III. positive feedback means connected in circuit between the bases of said four transistors and said output connection points Qa and Qb, said feedback means operative to provide current drive to the bases of said four transistors in cyclic alternation between transistors Qax and Qby, and transistors Qay and Qbx, whereby transistors Qax and Qby are rendered conductive in alternating fashion with transistors Qdx and Qay, the length of the period during which transistor Qax is rendered conductive being distinctly different from that during which Qby is rendered conductive, and the length of the period during which transistor Qbx is rendered conductive being distinctly different from that during which Qay is rendered conductive; whereby said AC output voltage, which is provided between connection points Qa and Qb, may be characterized by four cyclically re-occurring time periods: (i) a first period of a substantially constant-magnitude positive voltage, (ii) a second period of substantially zero-magnitude voltage, (iii) a third period of a substantially constant-magnitude negative voltage, and (iv) a fourth period of substantially zero-magnitude voltage.

Claim 15

A controlled inverter adapted to be powered from a DC source and to provide an AC voltage across a pair of output terminals, said inverter comprising: switching transistors arranged in push-pull configuration and connection with said DC source, said push-pull configuration having a pair of output terminals, each one of said transistors being operative by way of a set of switching control input terminals to be switched between an ON-state and an OFF-state; and positive feedback switching control means connected in circuit between said output terminals and each one of said transistors' control input terminals and operative to control the ON-states and OFF-states of the transistors such that the voltage provided across said pair of output terminals can be characterized by four cylically re-occurring time periods; (i) a first period of a substantially constant-magnitude positive voltage, (ii) a second period of substantially zero-magnitude voltage, (iii) a third period of a substantially constant-magnitude negative voltage, and (iv) a fourth period of substantially zero-magnitude voltage.

Claim 16

A controlled inverter adapted to be powered from a DC source and to provide an AC voltage across a pair of output terminals, said inverter comprising: switching transistors arranged in push-pull configuration and connection with said DC source, said push-pull configuration having a pair of output terminals, each one of said transistors being operative by way of a set of switching control input terminals to be switched between an ON-state and an OFF-state; and positive feedback switching control means connected in circuit between said output terminals and each one of said transistors' control input terminals and operative to control the ON-states and OFF-states of the transistors such that the voltage provided across said pair of output terminals can be characterized by four cylically re-occurring time periods; (i) a first period of a substantially constant-magnitude positive voltage, (ii) a second period of substantially zero-magnitude voltage, (iii) a third period of a substantially constant-magnitude negative voltage, and (iv) a fourth period of substantially zero-magnitude voltage.