Reverse voltage clamp circuit

Claim 2

A reverse voltage clamp circuit for preventing the collector voltage of an output transistor from substantially crossing a voltage reference near ground potential, said reverse voltage clamp circuit being adapted to be coupled to a voltage source and including: a first clamping transistor having an emitter coupled to the collector of said output transistor; a first diode coupled to the base of said clamping transistor; and a reference voltage means coupled to the voltage source and to said first diode for establishing a reference voltage at the input to said first diode so as to keep the collector potential of said output transistor from substantially crossing the voltage reference near ground potential.

Claim 3

A reverse voltage clamp circuit as recited in claim 1 further comprising: a second diode coupled to the collector of said clamping transistor and adapted to be coupled to the voltage source.

Claim 4

A reverse voltage clamp circuit as recited in claim 2 wherein said reference voltage means includes: a second transistor having a collector adapted to be coupled to the voltage source and an emitter coupled to said first diode; a first resistor coupled between the base and the collector of said second transistor; a third transistor having a collector coupled to the base of said second transistor and an emitter coupled to the ground potential; a second resistor coupled between the emitter of said second transistor and the base of said third transistor; a third resistor coupled between the base of said third transistor and the ground potential; a fourth resistor coupled between said first diode and second resistor; and said reference voltage means being adapted to establish a voltage approximately equal to the voltage drop across two base-emitter junctions of a transistor at said first diode, thereby preventing the emitter of said first clamping transistor from having a voltage substantially below the ground potential.

Claim 5

A reverse voltage clamp circuit as recited in claim 3 wherein: said first, second and third resistors are pinch resistors formed by a region of a first conductivity type positioned between two regions of a second conductivity type.

Claim 6

A reverse voltage clamp circuit as recited in claim 4 wherein said first and third resistors have one portion of said region of said first conducting type at the same potential as an adjacent region of said second conductivity type.

Claim 7

A reverse voltage clamp circuit as recited in claim 5 wherein the second conductivity type of said second resistor is coupled to said fourth resistor.

Claim 8

A reverse voltage clamp circuit for preventing the collector of an output transistor from substantially crossing a reference voltage near ground potential, the collector of the output transistor being formed of an N-type conductivity epitaxial layer of an integrated circuit, said reverse voltage clamp circuit comprising: a first NPN clamping transistor having an emitter coupled to the collector of the output transistor; said first NPN clamping transistor having a collector adapted to be coupled to a voltage source; a first diode having a cathode coupled to the base of said clamping transistor; and a reference voltage means coupled to said voltage source and to ground potential for keeping the potential at the collector of said output transistor from substantially crossing a reference potential nearthe ground potential.

Claim 9

A reverse voltage clamp circuit for preventing the collector of an output transistor from substantially crossing a reference voltage near ground potential, the collector of the output transistor being formed of an N-type conductivity epitaxial layer of an integrated circuit, said reverse voltage clamp circuit comprising: a first NPN clamping transistor having an emitter coupled to the collector of the output transistor; said first NPN clamping transistor having a collector adapted to be coupled to a voltage source; a first diode having a cathode coupled to the base of said clamping transistor; and a reference voltage means coupled to said voltage source and to ground potential for keeping the potential at the collector of said output transistor from substantially crossing a reference potential nearthe ground potential.

Claim 10

A reverse voltage clamp circuit as recited in claim 7 further comprising: a second diode coupled between said clamping transistor and the voltage source and having a cathode coupled to the collector of said clamping transistor and an anode adapted to be coupled to the voltage source.

Claim 11

A reverse voltage clamp circuit as recited in claim 8 wherein said reference voltage means includes: a second NPN transistor having a collector adapted to be coupled to the voltage source and an emitter coupled to said first diode;

Claim 12

a first P-type pinch resistor with end terminals coupled between the base and the collector of said second transistor and with an N-type plate terminal coupled to the collector of said second transistor; a third NPN transistor having a collector coupled to the base of saidsecond transistor and an emitter coupled to the ground potential; a second P-type pinch resistor with end terminals coupled between the emitter of said second transistor and the base of said third transistor, and with an N-type plate terminal; a third P-type pinch resistor with end terminals coupled between the base and the emitter of said third transistor; a fourth N-type epitaxial resistor coupled between the emitter of said second transistor and the plate terminal of said second P-type pinch resistor; and said second and third resistors having substantially the same magnitude so that there is established a reference voltage of about two times the voltage drop across the base-emitter junction of said third transistor at the anode of said first diode so as to keep the collector of said output transistor at or above ground.

Claim 13

a first P-type pinch resistor with end terminals coupled between the base and the collector of said second transistor and with an N-type plate terminal coupled to the collector of said second transistor; a third NPN transistor having a collector coupled to the base of saidsecond transistor and an emitter coupled to the ground potential; a second P-type pinch resistor with end terminals coupled between the emitter of said second transistor and the base of said third transistor, and with an N-type plate terminal; a third P-type pinch resistor with end terminals coupled between the base and the emitter of said third transistor; a fourth N-type epitaxial resistor coupled between the emitter of said second transistor and the plate terminal of said second P-type pinch resistor; and said second and third resistors having substantially the same magnitude so that there is established a reference voltage of about two times the voltage drop across the base-emitter junction of said third transistor at the anode of said first diode so as to keep the collector of said output transistor at or above ground.

Claim 14

A reverse voltage circuit as recited in claim 9 wherein said first and second diodes are base-collector junctions.