Apparatus for rapid execution of interrupts after the recognition of an interrupt request

Claim 1

A circuit arrangement for the rapid execution of interrupts after recognition of interrupt requests in a proccessor which comprises a control unit, control lines and a but connected to said control unit and an external program memory connected to said bus and storing an external program and in which instructions for executing and processing interrupts are inserted between instructions for working off a program, in which the inserted instructions are addressed with a plurality of instruction indicators which work in parallel and which are addressable in parallel, and in which the instruction indicators are addressed, on the one hand, by a program and, on the other hand, by recognition of interrupt requests, comprising: an interrupt multiplexer connected to said bus and including inputs for receiving interrupt requests; a circulating counter connected to said bus and operable to form addresses of said inputs and search said interrupt multiplexer for set interrupt requests; a multilevel interrupt register connected to said bus for storing interrupt requests under specific address as U-bits in a level determined by the address; a program register connected to said bus for storing and erasing P-bits in response to instructions of the external program in said external program memory; a program memory connected to said program register and to said interrupt register and storing an internal program for controlling the operation of said circuit arrangement; status register means connected to said control unit, to said circulating counter and to said program memory and operable to indicate the operational states of the search operation; means connected to said status register means and including said circulating counter, said interrupt register and said program register, operable to search for set U-bits and P-bits as a function of the states of said status register means; an address buffer connected to said bus and operable to store circulating counter addresses in response to the finding of U-bits and P-bits; an address register connected to said address buffer for storing the address stored in the address buffer at the end of each instruction worked off by said processor; and instruction indicator means connected to said bus and to said address register for providing parallel instruction indicators to said external program memory in response to the current address in said address register.