US4499419A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Methods and apparatus for assessing the quality of logic signals
Assignee: Gemalto Terminals Ltd
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Filing: 1981-06-15
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Granted: 1985-02-12
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Expires: 2001-06-15
Abstract
Abstract Departure of a logic signal from the ranges of signal values corresponding to defined logic levels is monitored by comparing the logic signal with the boundary values of these ranges. Provided the logic signal between transitions is below the lower threshold (14) or above the upper threshold (12), a NOR gate (16) and a D-type bistable circuit (18) open an AND gate (22) to enable a counter (24) to count 10 MHz clock pulses. If the logic signal is between the thresholds, the AND gate disables the counter. The four most significant digits of the total number of clock pulses actually counted after 1,000,000 have been supplied is displayed, giving an indication of the percentage of time for which the logic signal has a value corresponding to a defined logic level. As an alternative, the output signal of the NOR gate (16) can be inverted (26) and supplied to a moving-coil or digital voltmeter (30).
Inventors
- 👤 Charles Bockett-Pugh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 10:56
CPC Classifications
G; G01; G01R; G01R29/00; G01R29/02; G01R29/027; G01R19/00; G01R19/165; G01R19/16566; G01R19/16576; G01R19/1658; G01R19/17
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
170 words
A method of assessing the quality of a logic signal, comprising the steps of: generating a first threshold signal corresponding to a lower limiting value below which said logic signal represents a first defined logic state; generating a second threshold signal corresponding to an upper limiting value above which said logic signal represents a second defined logic state; comparing said logic signal with said first threshold signal and generating an output signal indicative of whether said logic signal is below said lower limiting value; comparing said logic signal with said second threshold signal and generating an output signal indicative of whether said logic signal is above said upper limiting value; combining said output signals, to generate a control signal indicative of whether said logic signal lies within a range of signal values, between said lower and upper limiting values, not corresponding to any defined logic state; and integrating said control signal with respect to time, whereby the magnitude of the integral is indicative of the quality of the logic signal.
Claim 2
Independent Claim
170 words
A method of assessing the quality of a logic signal, comprising the steps of: generating a first threshold signal corresponding to a lower limiting value below which said logic signal represents a first defined logic state; generating a second threshold signal corresponding to an upper limiting value above which said logic signal represents a second defined logic state; comparing said logic signal with said first threshold signal and generating an output signal indicative of whether said logic signal is below said lower limiting value; comparing said logic signal with said second threshold signal and generating an output signal indicative of whether said logic signal is above said upper limiting value; combining said output signals, to generate a control signal indicative of whether said logic signal lies within a range of signal values, between said lower and upper limiting values, not corresponding to any defined logic state; and integrating said control signal with respect to time, whereby the magnitude of the integral is indicative of the quality of the logic signal.
Claim 3
Dependent Claim
38 words
A method according to claim 1, wherein said integrating step comprises the steps of: supplying clock pulses at a predetermined rate; and counting said clock pulses in accordance with said control signal during a period of predetermined duration.
Claim 4
Dependent Claim
36 words
A method according to claim 2, wherein said control signal is arranged to cause said clock pulses to be counted when said logic signal is below said lower limiting value or above said upper limiting value.
Claim 5
Dependent Claim
24 words
A method according to claim 1, wherein said integrating step comprises supplying a current in accordance with said control signal to current measuring apparatus.
Claim 6
Dependent Claim
222 words
Apparatus for assessing the quality of a logic signal, comprising: means for generating a first threshold signal corresponding to a lower limiting value below which said logic signal represents a first defined logic state; means for generating a second threshold signal corresponding to an upper limiting value above which said logic signal represents a second defined logic state; first comparison means receiving said logic signal and coupled to said first signal generating means, for comparing said logic signal with said first threshold signal and generating an output signal indicative of whether said logic signal is below said lower limiting value; second comparison means receiving said logic signal and coupled to said second signal generating means, for comparing said logic signal with said second threshold signal and generating an output signal indicative of whether said logic signal is above said upper limiting value; means coupled to said first and second comparison means for combining the output signals thereof, to generate a control signal indicative of whether said logic signal lies within a range of signal values, between said lower and upper limiting values, not corresponding to any defined logic state; and means coupled to said control signal generating means for integrating said control signal with respect to time, whereby the magnitude of the integral is indicative of the quality of the logic signal.
Claim 7
Dependent Claim
222 words
Apparatus for assessing the quality of a logic signal, comprising: means for generating a first threshold signal corresponding to a lower limiting value below which said logic signal represents a first defined logic state; means for generating a second threshold signal corresponding to an upper limiting value above which said logic signal represents a second defined logic state; first comparison means receiving said logic signal and coupled to said first signal generating means, for comparing said logic signal with said first threshold signal and generating an output signal indicative of whether said logic signal is below said lower limiting value; second comparison means receiving said logic signal and coupled to said second signal generating means, for comparing said logic signal with said second threshold signal and generating an output signal indicative of whether said logic signal is above said upper limiting value; means coupled to said first and second comparison means for combining the output signals thereof, to generate a control signal indicative of whether said logic signal lies within a range of signal values, between said lower and upper limiting values, not corresponding to any defined logic state; and means coupled to said control signal generating means for integrating said control signal with respect to time, whereby the magnitude of the integral is indicative of the quality of the logic signal.
Claim 8
Dependent Claim
40 words
Apparatus according to claim 5, wherein said integrating means comprises: means arranged to supply clock pulses at a predetermined rate; and means arranged to count said clock pulses in accordance with said control signal during a period of predetermined duration.
Claim 9
Dependent Claim
37 words
Apparatus according to claim 6, wherein said control signal is arranged to cause said counting means to count said clock pulses when said logic signal is below said lower limiting value or above said upper limiting value.
Claim 10
Dependent Claim
26 words
Apparatus according to claim 5, wherein said integrating means comprises: means arranged to supply a current in accordance with said control signal; and current measuring apparatus.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-02-12 | 1988-08-13 | 1989-02-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-02-12 | 1992-08-13 | 1993-02-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-02-12 | 1996-08-13 | 1997-02-12 | $7700.00 | Window Closed / Lapsed |