Self-clocking binary receiver

Claim 2

In a data receiver for receiving input binary data in which 1 and 0 logic levels are represented by signals having first and second different pulsewidths, respectively, said receiver comprising means responsive to the received input binary data for integrating the same and for producing corresponding signals of first and second levels, means coupled to said integrating means for establishing from said integrated signals clock-control signals at a first node and data-control signals at a second node, and first and second switching means respectively connected to said first and second nodes for respectively producing at their outputs a clock signal for each input data signal and a data signal for each input data signal at only one of said first and said second pulsewidths.

Claim 3

The data receiver of claim 1, in which said signalestablishing means comprises a voltage divider including said first and second nodes, said data-control signals at said second node being a predetermined ratio of said clock-control signals at said first node.

Claim 4

The data receiver of claim 2, further comprising a flip-flop having first and second inputs connected respectively to the outputs of said first and second switching means, and a shift register having a data input connected to the output of said flip-flop and a clock input operatively connected to the output of said second switching means.

Claim 5

In a data receiver for receiving input binary data in which 1 and 0 logic levels are represented by signals having first and second different pulsewidths, respectively, said receiver comprising means for integrating the received input binary data and for producing corresponding signals of first and second voltage levels, means coupled to said integrating means for establishing from said integrated signals clock control signals at a first node and reduced voltage level data control signals at a second node, and first and second switching means respectively connected to said first and second nodes, said first and second switching means having predetermined threshold levels, thereby acting as gates such that said data control signals corresponding to one of said pulsewidths is sufficiently high to activate said second switching means inducing an output from said switching means, whereas the voltage level of said data control signal established at said second node in corresponding to one of the other of said pulsewidths is less than that required to activate said second switching means.

Claim 6

In a data receiver for receiving input binary data in which 1 and 0 logic levels are represented by signals having first and second different pulsewidths, respectively, said receiver comprising means for integrating the received input binary data and for producing corresponding signals of first and second voltage levels, means coupled to said integrating means for establishing from said integrated signals clock control signals at a first node and reduced voltage level data control signals at a second node, and first and second switching means respectively connected to said first and second nodes, said first and second switching means having predetermined threshold levels, thereby acting as gates such that said data control signals corresponding to one of said pulsewidths is sufficiently high to activate said second switching means inducing an output from said switching means, whereas the voltage level of said data control signal established at said second node in corresponding to one of the other of said pulsewidths is less than that required to activate said second switching means.

Claim 7

The data receiver of claim 4, in which the voltage level of the clock-control signal established at said first node in response to an input data signal of either of said first and second pulsewidths is sufficient to activate said first switching means which act as a gate, thereby to produce a clock signal at the output of said first switching means.

Claim 8

The data receiver of claim 4, in which said signal establishing means comprises a voltage divider including said first and second nodes, said data-control signals at said second node being a predetermined ratio of said clock control signal at said first node.

Claim 9

In a receiver for receiving binary data in which incoming signals have a first pulsewidth indicative of one logic state and a second pulsewidth indicative of a second logic state, self clocking circuitry for producing distinct clock and data signals from said incoming data comprising: (a) input means for introducing said incoming data to said circuitry; (b) integrator means electrically coupled to said input means and directly responsive to said incoming data for generating integrated signals corresponding to signals included in said incoming data, said integrated signals being characterized by a first pulse height characteristic of one logic state and a second pulse height characteristic of a second logic state, said pulse heights and said integrated signals respectively corresponding to the pulsewidth of said incoming signals; (c) means for attenuating said integrated signals electrically coupled to an output of said integrator means, said attenuated integrated signals corresponding to said integrated signals and having a lower pulse height; (d) first gate means directly electrically coupled to an output of said integrator means for producing a clock signal corresponding to each of said integrated signals, which in turn, correspond to the pulsewidths of said incoming signals and; (e) second gate means electrically coupled to said attenuating means having an excitation threshold higher than the pulse height of some of said attenuated integrated signals, whereby a data signal is selectively produced at the output of said second gate means, and some of said incoming signals cause no output from said second gate means.

Claim 10

In a receiver for receiving binary data in which incoming signals have a first pulsewidth indicative of one logic state and a second pulsewidth indicative of a second logic state, self clocking circuitry for producing distinct clock and data signals from said incoming data comprising: (a) input means for introducing said incoming data to said circuitry; (b) integrator means electrically coupled to said input means and directly responsive to said incoming data for generating integrated signals corresponding to signals included in said incoming data, said integrated signals being characterized by a first pulse height characteristic of one logic state and a second pulse height characteristic of a second logic state, said pulse heights and said integrated signals respectively corresponding to the pulsewidth of said incoming signals; (c) means for attenuating said integrated signals electrically coupled to an output of said integrator means, said attenuated integrated signals corresponding to said integrated signals and having a lower pulse height; (d) first gate means directly electrically coupled to an output of said integrator means for producing a clock signal corresponding to each of said integrated signals, which in turn, correspond to the pulsewidths of said incoming signals and; (e) second gate means electrically coupled to said attenuating means having an excitation threshold higher than the pulse height of some of said attenuated integrated signals, whereby a data signal is selectively produced at the output of said second gate means, and some of said incoming signals cause no output from said second gate means.

Claim 11

The data receiver of claim 7, wherein said integrator means comprise an R-C circuit, and said attenuating means comprise a resistor ladder type of circuitry.

Claim 12

The data receiver of claim 7, wherein said first and said second gate means comprise CMOS buffers.

Claim 13

The data receiver of claim 7, further comprising a flip-flop having first and second inputs respectively connected to outputs of said first and second gate means, and a shift register having data input connected to the output of said flip-flop and a clock input connected to the output of said second switching means.