US4495531A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Equalizer circuit for signal waveform reproduced by apparatus for magnetic digital data recording and playback
Assignee: Victor Company of Japan Ltd
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Filing: 1983-03-08
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Granted: 1985-01-22
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Expires: 2003-03-08
Abstract
Abstract In an apparatus for magnetic digital data recording and playback, a waveform equalizer circuit thins a signal reproduced from a magnetic recording medium in order to correct a waveform of the signal. Both the gain and phase are designed variable during recording and reproduction of the digital signal, so that the reproduced signal can be equalized under any desired frequency and phase characteristics without intercode interference among solitary waveforms which appear upon magnetic flux reversals.
Inventors
- 👤 Kouhei Sasamura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 08:19
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B5/00; G11B5/02; G11B5/027; G11B5/035
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
118 words
An apparatus for equalizing the waveform of a signal reproduced from a magnetic recording medium, comprising: a phase circuit for varying a phase of a signal passing therethrough; an adder circuit for processing the reproduced signal whose waveform is to be equalized; a first integrator circuit for integrating an output signal of said adder circuit and varying an integration time constant thereof; a second integrator circuit for integrating an output signal of said first integration circuit; and a coefficient circuit for adjusting the level of an output signal of said second integrator circuit and supplying an output signal thereof to the adder circuit, the adder circuit processing the reproduced signal and the output signal of said coefficient circuit.
Claim 2
Independent Claim
118 words
An apparatus for equalizing the waveform of a signal reproduced from a magnetic recording medium, comprising: a phase circuit for varying a phase of a signal passing therethrough; an adder circuit for processing the reproduced signal whose waveform is to be equalized; a first integrator circuit for integrating an output signal of said adder circuit and varying an integration time constant thereof; a second integrator circuit for integrating an output signal of said first integration circuit; and a coefficient circuit for adjusting the level of an output signal of said second integrator circuit and supplying an output signal thereof to the adder circuit, the adder circuit processing the reproduced signal and the output signal of said coefficient circuit.
Claim 3
Dependent Claim
16 words
An apparatus as claimed in claim 1, further comprising an input terminal and an output terminal.
Claim 4
Dependent Claim
54 words
An apparatus as claimed in claim 2, in which the input terminal is directly connected to the phase circuit while the output terminal is connected to the first integrator circuit, the reproduced signal being delivered and processed as passing through the phase circuit, the adder circuit and the first integrator circuit in this sequence.
Claim 5
Dependent Claim
53 words
An apparatus as claimed in claim 2, in which the input terminal is directly connected to the adder circuit while the output terminal is connected to the phase circuit, the reproduced signal being delivered and processed as oassing through the adder circuit, the first integrator circuit and the phase circuit in this sequence.
Claim 6
Dependent Claim
21 words
An apparatus as claimed in claim 1, further comprising a third integrator circuit which is directly connected to the phase circuit.
Claim 7
Dependent Claim
16 words
An apparatus as claimed in claim 5, further comprising an input terminal and an output terminal.
Claim 8
Dependent Claim
58 words
An apparatus as claimed in claim 6, in which the input terminal is directly connected to the phase circuit while the output terminal is connected to the first integrator circuit, the reproduced signal being delivered and processed as passing through the phase circuit, the third integrator circuit, the adder circuit and the first integrator circuit in this sequence.
Claim 9
Dependent Claim
58 words
An apparatus as claimed in claim 6, in which the input terminal is directly connected to the adder circuit while the output terminal is connected to the third integrator circuit, the reproduced signal being delivered and processed as passing through the adder circuit, the first integrator circuit, the phase circuit and the third integrator circuit in this sequence.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-01-22 | 1988-07-23 | 1989-01-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-01-22 | 1992-07-23 | 1993-01-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-01-22 | 1996-07-23 | 1997-01-22 | $7700.00 | Window Closed / Lapsed |