US4495468A
Expired / Lapsed
US
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Controlled phase off-set digital test system
Assignee: SPX Technologies Inc
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Filing: 1981-01-02
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Granted: 1985-01-22
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Expires: 2001-01-02
Abstract
Abstract In the testing of a digital test system (e.g. the automatic testing of a digital integrated semiconductor circuit) it is necessary to provide a plurality of clock signals (periodic pulse signals), each with a definite phase relationship to a particular clock signal called the "reference". For example, when the clock signals are all in the same phase they define a common wavefront without skew. The present invention produces a clock output signal that is offset in phase with respect to the reference according to a phase offset control signal by feeding the clock input to a voltage controlled variable phase shifter, comparing the shifted clock output signal with the reference to produce an output representative of the phase difference that is fed to a negative feedback circuit that controls the variable phase shifter and means are provided in the feedback circuit for modifying the feedback according to the offset control signal so that the clock output phase offset is proportional to the offset control signal when the system is in equilibrium.
Inventors
- 👤 Edward W. Richards
- 👤 Paul T. Chang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 20:50
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/135; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0816
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
138 words
A system for producing a clock output signal that is offset in phase with respect to a reference signal according to a clock phase offset control signal comprising; (a) sources of clock and reference signals and clock offset control signal, (b) a controlled variable phase shifter for shifting phase of the clock signal, producing a clock output signal, (c) a phase comparator for comparing the phase shifted clock output signal with the reference signal producing a comparator output signal representative of the phase difference, (d) a negative feedback circuit between the comparator output and the variable phase shift control and (e) means in said feedback circuit for multiplying feedback to the phase shifter by the off-set control signal, (f) whereby the clock output phase offset is proportional to the offset control signal when the system is in equilibrium.
Claim 2
Independent Claim
138 words
A system for producing a clock output signal that is offset in phase with respect to a reference signal according to a clock phase offset control signal comprising; (a) sources of clock and reference signals and clock offset control signal, (b) a controlled variable phase shifter for shifting phase of the clock signal, producing a clock output signal, (c) a phase comparator for comparing the phase shifted clock output signal with the reference signal producing a comparator output signal representative of the phase difference, (d) a negative feedback circuit between the comparator output and the variable phase shift control and (e) means in said feedback circuit for multiplying feedback to the phase shifter by the off-set control signal, (f) whereby the clock output phase offset is proportional to the offset control signal when the system is in equilibrium.
Claim 3
Dependent Claim
51 words
A system as in claim 1 wherein the feedback circuit includes, (a) signal level storage means for storing the comparator output signal level, (b) the multiplyer circuit for multiplying the stored signal level by the offset control signal and (c) means for coupling the multiplier output to the phase shifter control.
Claim 4
Dependent Claim
79 words
A system as in claim 2 wherein (a) means are provided for shifting phase of the reference signal a maximum shift that corresponds to the maximum offset control signal and (b) control switching means are provided in the system so that the reference signal is phase shifted said maximum shift when the comparator output is coupled to the storing means and the reference signal is not phase shifted when the comparator output is not coupled to the storing means.
Claim 5
Dependent Claim
24 words
A system as in claim 3 wherein the storing means stores the voltage level of the comparator output when the switching means is activated.
Claim 6
Dependent Claim
45 words
A system as in claim 3 wherein (a) other storage means is provided for storing the comparator output signal level when the reference signal is not phase shifted and (b) other means is provided for coupling the output thereof to the variable phase shifter control.
Claim 7
Dependent Claim
30 words
A system as in claim 5 wherein means are provided for combining the multiplier output and the other storage output and applying the combination to the variable phase shifter control.
Claim 8
Dependent Claim
47 words
A system as in claim 6 wherein the switching means includes a switch between the comparator output and the first mentioned and other storing means and a switch between the reference signal input to the comparator and the reference signal with maximum shift and with no shift.
Claim 9
Dependent Claim
17 words
A system as in claim 7 wherein means are provided for operating said switching means in unison.
Claim 10
Dependent Claim
36 words
A system as in claim 8 wherein means are provided for varying the offset control signal to thereby vary the clock output signal phase offset when the comparator output is not coupled to either storing means.
Claim 11
Independent Claim
117 words
A method of producing a clock output signal that is offset in phase according to an offset control signal with respect to a reference signal comprising the steps of: (a) shifting the phase of the clock signal, (b) comparing the phase of the phase shifted clock signal with the phase of the reference signal to produce a comparison output signal representative of the difference in phase, (c) multiplying said output signal by the offset control signal producing a modified comparison output signal and (d) controlling said clock signal phase shifting with said modified output signal, (e) whereby the clock output signal is offset in phase with respect to the reference signal according to the offset control signal.
Claim 12
Independent Claim
117 words
A method of producing a clock output signal that is offset in phase according to an offset control signal with respect to a reference signal comprising the steps of: (a) shifting the phase of the clock signal, (b) comparing the phase of the phase shifted clock signal with the phase of the reference signal to produce a comparison output signal representative of the difference in phase, (c) multiplying said output signal by the offset control signal producing a modified comparison output signal and (d) controlling said clock signal phase shifting with said modified output signal, (e) whereby the clock output signal is offset in phase with respect to the reference signal according to the offset control signal.
Claim 13
Dependent Claim
54 words
The method as in claim 10 including the step of deskewing by: (a) storing the comparison output signal from the comparing step, while the offset control signal is at zero value and the shift in phase of the reference signal is zero and (b) controlling the clock signal shifting with the said stored signal.
Claim 14
Dependent Claim
48 words
The method as in claim 10 including the steps of: (a) shifting the phase of the reference signal a maximum shift that corresponds to the maximum offset control signal before comparing with the phase shifted clock output signal and (b) storing the output signal from the comparing step.
Claim 15
Dependent Claim
64 words
The method as in claim 12 wherein: (a) the reference signal is shifted in phase a maximum shift while the offset control signal is set at its maximum (b) the comparing output is stored, (c) the stored signal is multiplied by the maximum offset control signal and (d) the product thereof is applied to control the shifting of the phase of the clock signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-01-22 | 1988-07-23 | 1989-01-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-01-22 | 1992-07-23 | 1993-01-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-01-22 | 1996-07-23 | 1997-01-22 | $7700.00 | Window Closed / Lapsed |