Abstract An anti-howl back device which includes various devices and a CPU that controls these devices, their decisions, and their processings in order to output the signals which are fed into a selector circuit upon the removal of acoustic feedback components in a manner that makes a decision on presence of a synchronous signal and an address signal in combination in the output from the selector circuit. Upon the affirmative result of such a decision, an A-D converter carries out an A-D conversion of the sample obtained by a sampling performed in synchronism with a synchronous signal and then subtracts the data which has been fetched from an address in a memory system corresponding to the address signal in combination with the synchronous signal from the data derived as a result of the A-D conversion. The new data thus obtained is then stored in the memory system while being concurrently delivered to a D-A converter. A multiplexer then carries out an addition to the output from the D-A converter of the synchronous signal and the address signal corresponding to the address of the new data that has been stored in the memory system. Upon a negative result of the decision, the A-D converter carries out an A-D conversion of the sample obtained by a sampling performed by a given timing and then stores the new data thus obtained in the memory system while concurrently delivering such new data to the D-A converter. A multiplexer adds to the output from the D-A converter the synchronous signal and the address signal corresponding to the address of said new datum that has been planted in the memory system.
An anti-howl back device comprising: a selector circuit for separating an input signal into a combination signal comprising a synchronous signal and an address signal and into an audio signal; an A-D converter connected to said selector circuit for providing an A-D conversion of said audio signal; a CPU connected to said A-D converter and said selector circuit; a D-A converter connected to said CPU for providing a D-A conversion of signals which have been processed by said CPU; a multiplexer for adding said combination signal comprising a synchronous signal and an address signal to an output signal from said D-A converter; a memory system connected to said CPU for storing a program for operating said CPU and for storing data processed by said CPU; wherein said CPU makes a decision on the presence of said combination signal which is output from said selector circuit and, upon an affirmative result of such a decision, causes said A-D converter to carry out an A-D conversion of a sample of said audio signal obtained by a sampling performed in synchronism with said synchronous signal, and subtracts data fetched from an address in said memory system corresponding to said address signal which is combined with said synchronous signal from data which has been derived as a result of said A-D conversion, and stores new data corresponding to said subtraction in said memory system while concurrently feeding said new data to said D-A converter, and then causes said multiplexer to add an output from said D-A converter to said combination signal comprising said synchronous signal and said address signal and corresponding to the address of said new data that has been stored in said memory system; and, upon a negative result of such a decision, causes said A-D converter to carry out an A-D conversion of said audio sample and stores such new data thus obtained in said memory system while concurrently feeding such new data to said D-A converter, and then causes said multiplexer to add an output from said D-A converter to said combination signal comprising said synchronous signal and said address signal and corresponding to said address of said new data that has been stored in said memory system.
Claim 2
Dependent Claim
368 words
An anti-howl back device comprising: a selector circuit for separating an input signal into a combination signal comprising a synchronous signal and an address signal and into an audio signal; an A-D converter connected to said selector circuit for providing an A-D conversion of said audio signal; a CPU connected to said A-D converter and said selector circuit; a D-A converter connected to said CPU for providing a D-A conversion of signals which have been processed by said CPU; a multiplexer for adding said combination signal comprising a synchronous signal and an address signal to an output signal from said D-A converter; a memory system connected to said CPU for storing a program for operating said CPU and for storing data processed by said CPU; wherein said CPU makes a decision on the presence of said combination signal which is output from said selector circuit and, upon an affirmative result of such a decision, causes said A-D converter to carry out an A-D conversion of a sample of said audio signal obtained by a sampling performed in synchronism with said synchronous signal, and subtracts data fetched from an address in said memory system corresponding to said address signal which is combined with said synchronous signal from data which has been derived as a result of said A-D conversion, and stores new data corresponding to said subtraction in said memory system while concurrently feeding said new data to said D-A converter, and then causes said multiplexer to add an output from said D-A converter to said combination signal comprising said synchronous signal and said address signal and corresponding to the address of said new data that has been stored in said memory system; and, upon a negative result of such a decision, causes said A-D converter to carry out an A-D conversion of said audio sample and stores such new data thus obtained in said memory system while concurrently feeding such new data to said D-A converter, and then causes said multiplexer to add an output from said D-A converter to said combination signal comprising said synchronous signal and said address signal and corresponding to said address of said new data that has been stored in said memory system.
Claim 3
Dependent Claim
124 words
An anti-howl back device as claimed in claim 1, wherein said CPU makes a decision on presence of said combination signal comprising said synchronous signal and said address signal output from said selector circuit, feeds an audio sampling signal into a sampling circuit of said A-D converter and reads out data stored in an address corresponding to said address signal from said memory system and, while said A-D converter is converting said sampled audio signal, compares a level of said input synchronous signal with that of said synchronous signal output from said CPU so as to determine a proportional ratio, and subsequently corrects data thus fetched using said proportional ratio and then subtracts said data thus corrected from data output from said A-D converter.