US4493024A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital data processing system
Assignee: EMC Corp
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Filing: 1981-05-22
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Granted: 1985-01-08
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Expires: 2001-05-22
Abstract
Abstract A data processing system having a flexible internal structure, protected from and effecitvely invisible to users, with multilevel control and stack mechanisms and capability of performing multiple, concurrent operations, and providing a flexible, simplified interface to users. The system is internally comprised of a plurality of separate, independent processors, each having a separate microinstruction control and at least one separate, independent port to a central communications and memory node. The communications and memory node is an independent processor having separate, independent microinstruction control and comprised of a plurality of independently operating, microinstruction controlled processors capable of performing multiple, concurrent memory and communications operations. Addressing mechanisms allow permanent, unique identification of information and an extremely large address space accessible and common to all such systems. Addresses are independent of system physical configuration. Information is identified to bit granular level and to information type and format. Protection mechanisms provide variable access rights associated with individual bodies of information. User language instructions are transformed into dialect coded, uniform, intermediate level instructions to provide equal facility of execution for all user languages. Operands are referred to by uniform format names which are transformed, by internal mechanisms transparent to users, into addresses.
Inventors
- 👤 II Ward Baxter
- 👤 Gerald F. Clancy
- 👤 Ronald H. Gruner
- 👤 Craig J. Mundie
- 👤 Brett L. Bachman
- 👤 Stephen R. Redfield
- 👤 William N. Coder
- 👤 Thomas M. Jones
- 👤 David L. Houseman
- 👤 Charles J. Young
- 👤 Steven M. Haeffele
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 12:38
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30181; G06F9/30192; G06F9/34; G06F9/35
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
217 words
A digital computer system, comprising: processor means for performing operations upon operands, memory means for storing said operands and instructions for directing the operations of said processor means, said processor means responsive to the instructions directing said operations, bus means for conducting instructions and operands between said memory means and said processor means, and I/O means for conducting operands between said memory means only and devices external to said digital computer system, said bus means including memory output bus means connected from a first part of said memory means to said processor means for conducting instructions and operands from said memory means to said processor means processor output bus means connected from said processor means to a second part of said memory means for conducting the results of operations from said processor means to said memory means, and address bus means connected from said processor means to an address input of said memory means to conduct first addresses from said processor means to said memory means, said memory means responsive to said first addresses to read instructions and operands corresponding thereto from said memory means to said processor means, and said processor means further including addressing means connected to said address bus means and responsive to the operation of said processor means to provide said first addresses.
Claim 2
Dependent Claim
217 words
A digital computer system, comprising: processor means for performing operations upon operands, memory means for storing said operands and instructions for directing the operations of said processor means, said processor means responsive to the instructions directing said operations, bus means for conducting instructions and operands between said memory means and said processor means, and I/O means for conducting operands between said memory means only and devices external to said digital computer system, said bus means including memory output bus means connected from a first part of said memory means to said processor means for conducting instructions and operands from said memory means to said processor means processor output bus means connected from said processor means to a second part of said memory means for conducting the results of operations from said processor means to said memory means, and address bus means connected from said processor means to an address input of said memory means to conduct first addresses from said processor means to said memory means, said memory means responsive to said first addresses to read instructions and operands corresponding thereto from said memory means to said processor means, and said processor means further including addressing means connected to said address bus means and responsive to the operation of said processor means to provide said first addresses.
Claim 3
Dependent Claim
183 words
A digital computer system, comprising: processor means for performing operations upon operands, memory means for storing operands and instructions for directing the operations of said processor means, said processor means responsive to the instructions directing said operations, bus means for conducting instructions and operands between said memory means and said processor means, and I/O means for conducting operands between said memory means and devices external to said digital computer system, said I/O means including: channel means connected from said external devices for conducting operands to and from said external devices, I/O bus means connected between said channel means and a selected part of said memory means for conducting operands between said channel means and said memory means, and addressing means connected to said I/O bus means and responsive to the operation of said channel means and said memory means for providing addresses for controlling the reading of operands from said memory means and the writing of operands into said memory means, said memory means and said channel means responsive to said addresses for conducting operands between said memory means and said external devices.
Claim 4
Dependent Claim
183 words
A digital computer system, comprising: processor means for performing operations upon operands, memory means for storing operands and instructions for directing the operations of said processor means, said processor means responsive to the instructions directing said operations, bus means for conducting instructions and operands between said memory means and said processor means, and I/O means for conducting operands between said memory means and devices external to said digital computer system, said I/O means including: channel means connected from said external devices for conducting operands to and from said external devices, I/O bus means connected between said channel means and a selected part of said memory means for conducting operands between said channel means and said memory means, and addressing means connected to said I/O bus means and responsive to the operation of said channel means and said memory means for providing addresses for controlling the reading of operands from said memory means and the writing of operands into said memory means, said memory means and said channel means responsive to said addresses for conducting operands between said memory means and said external devices.
Claim 5
Dependent Claim
125 words
The digital computer system of claim 1, wherein said I/O means further comprises: channel means connected from said external devices for conducting operands to and from said external devices, I/O bus means connected between said channel means and a third part of said memory means for conducting operands between said channel means and said memory means, and I/O addressing means connected to said I/O bus means and responsive to the operation of said channel means and said memory means for providing second addresses for controlling the reading of operands from said memory means and the writing of operands into said memory means, said memory means and said channel means responsive to said second addresses for conducting operands between said memory means and said external devices.
Claim 6
Dependent Claim
187 words
The digital computer system of claim 3, wherein: said processor means further comprises processor addressing means connected to said bus means and responsive to the operation of said processor means for providing first addresses for controlling the reading of instructions and operands from said memory storage means to said processor means and controlling the writing of the results of operations from said processor means to said memory storage means, said memory means is responsive to said first addresses to read instructions and operands from said memory storage means to said processor means and to write the results of operations from said processor means to said memory storage means, and said I/O addressing means connected to said channel means and responsive to the operation of said memory means and said channel means for providing second addresses for controlling the conducting of operands between said memory storage means and said external devices, said memory means and said channel means responsive to said second addresses to write operands from said channel means to said memory storage means and to read operands from said memory storage means to said channel means.
Claim 7
Dependent Claim
190 words
The digital computer system of claim 4, wherein: said processor means further comprises processor interrupt means responsive to operation of said processor means for generating processor interrupt signals indicating that certain of said operands or certain of said instructions for said operations are not currently stored in said memory storage means, said I/O means further comprises I/O interrupt means for generating I/O interrupt signals indicating that said certain of said operands or said certain of said instructions have been conducted from said external devices and written into said memory storage means, and said digital computer system further comprises interrupt bus means connected between said processor interrupt means and said I/O means for conducting said processor interrupt signals and said I/O interrupt signals between said processor interrupt means and said I/O means, said I/O means responsive to said processor interrupt signals to conduct said certain of said operands or said certain of said instructions from said external devices to said memory storage means and said processor means responsive to said I/O interrupt signals to read said certain of said operands or said certain of said instructions from said memory storage means.
Claim 8
Dependent Claim
128 words
The digital computer system of claim 5, wherein: said processor addressing means is responsive to operation of said processor means and said memory means to provide first certain of said first addresses comprising requests for said certain of said operands or certain of said instructions required for said operations and not presently stored in said memory storage means, said memory means is responsive to operation of said processor means and said I/O means to provide first certain of said second addresses corresponding to said certain of said first addresses to said I/O means, and I/O means is responsive to said first certain of said second addresses to write said certain of said operands or said certain of said instructions from said external devices into said memory storage means.
Claim 9
Dependent Claim
142 words
The digital computer system of claim 6, wherein: said memory means includes means for storing information regarding operands and instructions stored in said memory storage means, said processor means is responsive to information concerning third certain of said instructions to generate third certain of said first addresses comprising requests to transfer second certain of said operands or said instructions between said memory storage means and said external devices, said memory means is responsive to said third certain of said first addresses to provide corresponding second certain of said second addresses to said I/O means, said memory means is further responsive to said third certain of said first addresses and said I/O means is responsive to said second certain of said second addresses to transfer said second certain of said operands or said instructions between said memory storage means and said external devices.
References Cited (Backward Citations)
US4228496A
Cited
US4128876A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-01-08 | 1988-07-09 | 1989-01-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-01-08 | 1992-07-09 | 1993-01-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-01-08 | 1996-07-09 | 1997-01-08 | $7700.00 | Window Closed / Lapsed |