High resolution digital-to-analog converter

Claim 2

In a two-stage digital-to-analog converter wherein the first stage decodes a set of higher-order bits and the second stage decodes the remaining, lower-order bits, said second stage including an output generating circuit, said first stage comprising a series-connected string of resistors energized, in operation, by a reference voltage and including first switch means responsive to said higher-order bits for stepping up or down the string of resistors to make first and second connections respectively to any pair of adjacent nodal points of said resistor string to produce between first and second reference leads any of the voltages appearing across the resistors of said string; first and second buffer amplifiers having input circuits connected to said reference leads respectively responsive to the selected nodal point voltages to develop a voltage for the input of said second-stage of the converter; said first switch means being operable at each step up (or down) the resistor string to interchange the roles of said buffer amplifiers at each step up (or down) the resistor string by switching the connection to only one of said nodal points, connecting the corresponding buffer amplifier to the nodal point next beyond the nodal point to which the other buffer amplifier is connected while leaving said other buffer amplifier with its connection to the resistor string unchanged, whereby said buffer amplifiers are alternatingly connected to the successive nodal points of said resistor string as said first switch means steps the connections up (or down) the string; and means operable to interchange the roles of the buffer amplifiers relative to the output signal generating circuit of said second stage of the converter for each step up (or down) the resistor string effected by said first switch means; the interchanged roles of said buffer amplifiers produced by said alternating connection of said buffer amplifiers to said successive nodal points serving to minimize differential non-linearity errors which otherwise could occur due to offset mismatch between the buffer amplifiers.

Claim 3

In a two-stage digital-to-analog converter wherein the first stage decodes a set of higher-order bits and the second stage decodes the remaining, lower-order bits, said first stage comprising a series-connected string of resistors energized by a reference voltage and including first switch means responsive to said higher-order bits for stepping up or down the string of resistors to make first and second connections respectively to any pair of adjacent nodal points of said resistor string to produce between first and second reference leads any of the voltages appearing across the resistors of said string; first and second buffer amplifiers having input circuits connected to said reference leads respectively responsive to the selected nodal point voltages to develop a voltage for the input of said second-stage converter; said first switch means being operable at each step up (or down) the resistor string to interchange the roles of said buffer amplifiers at each step up (or down) the resistor string by switching the connection to only one of said nodal points, connecting the corresponding buffer amplifier to the nodal point next beyond the nodal point to which the other buffer amplifier is connected while leaving said other buffer amplifier with its connection to the resistor string unchanged, whereby said buffer amplifiers are alternatingly connected to the successive nodal points of said resistor string as said first switch means steps the connections up (or down) the string; means connecting the outputs of said buffer amplifiers to respective input terminals of the second stage of said converter; an R-2R series/shunt resistor ladder network for said second stage converter; a set of transistor switches each operable to connect a respective shunt resistor alternatively to one or the other of said input terminals in accordance with the binary state of an applied switch signal; an additional transistor switch operable to connect said terminating resistor alternatively to one or the other of said input terminals in accordance with the binary state of an applied switch signal; circuit means for coupling said lower-order bits to said set of transistor switches respectively; `said circuit means including logic means operable in response to the digital input signal to alternatingly (1) apply the lower-order bits directly to the set of switches, and (2) apply the complement of said bits to the set of switches, for each step (up or down) the resistor string effected by said first switch means; and means operable in synchronism with said first switch means for alternatingly operating said additional transistor switch for each step up (or down) the resistor string effected by said first switch means; the interchanged roles of said buffer amplifiers produced by said alternating connection of said buffer amplifiers to said successive nodal points serving to minimize differential non-linearity errors which otherwise could occur due to offset mismatch between the buffer amplifiers.

Claim 4

In a two-stage digital-to-analog converter wherein the first stage decodes a set of higher-order bits and the second stage decodes the remaining, lower-order bits, said first stage comprising a series-connected string of resistors energized by a reference voltage and including first switch means responsive to said higher-order bits for stepping up or down the string of resistors to make first and second connections respectively to any pair of adjacent nodal points of said resistor string to produce between first and second reference leads any of the voltages appearing across the resistors of said string; first and second buffer amplifiers having input circuits connected to said reference leads respectively responsive to the selected nodal point voltages to develop a voltage for the input of said second-stage converter; said first switch means being operable at each step up (or down) the resistor string to interchange the roles of said buffer amplifiers at each step up (or down) the resistor string by switching the connection to only one of said nodal points, connecting the corresponding buffer amplifier to the nodal point next beyond the nodal point to which the other buffer amplifier is connected while leaving said other buffer amplifier with its connection to the resistor string unchanged, whereby said buffer amplifiers are alternatingly connected to the successive nodal points of said resistor string as said first switch means steps the connections up (or down) the string; means connecting the outputs of said buffer amplifiers to respective input terminals of the second stage of said converter; an R-2R series/shunt resistor ladder network for said second stage converter; a set of transistor switches each operable to connect a respective shunt resistor alternatively to one or the other of said input terminals in accordance with the binary state of an applied switch signal; an additional transistor switch operable to connect said terminating resistor alternatively to one or the other of said input terminals in accordance with the binary state of an applied switch signal; circuit means for coupling said lower-order bits to said set of transistor switches respectively; `said circuit means including logic means operable in response to the digital input signal to alternatingly (1) apply the lower-order bits directly to the set of switches, and (2) apply the complement of said bits to the set of switches, for each step (up or down) the resistor string effected by said first switch means; and means operable in synchronism with said first switch means for alternatingly operating said additional transistor switch for each step up (or down) the resistor string effected by said first switch means; the interchanged roles of said buffer amplifiers produced by said alternating connection of said buffer amplifiers to said successive nodal points serving to minimize differential non-linearity errors which otherwise could occur due to offset mismatch between the buffer amplifiers.

Claim 5

Apparatus as claimed in claim 2, wherein said second-stage converter is a CMOS converter employing CMOS voltage switching.