US4491808A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Equalizer circuit for use in communication unit
Assignee: Mitsubishi Electric Corp
•
Filing: 1982-09-14
•
Granted: 1985-01-01
•
Expires: 2002-09-14
Abstract
Abstract An equalizer circuit for use in a communication unit comprises a variable amplitude equalizer (VAE) and a variable group delay equalizer (VDE). The variable amplitude equalizer (VAE) is able to vary only an amplitude frequency response continuously without varying a group delay frequency response, while the variable group delay equalizer (VDE) is able to vary only a group delay frequency response continuously without varying an amplitude frequency response, both being able to adjust the amplitude and group delay frequency responses, respectively, in an independent manner. Preferably, the variable group delay equalizer (VDE) includes an amplitude correcting portion and is structured such that amplitude distortion caused in a delay portion can be corrected by a signal from the amplitude correcting portion.
Inventors
- 👤 Kazuo Saito
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 04:34
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/03; H04L25/03006; H04L25/03012; H04L25/03114; H04L25/03133
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
262 words
A variable group delay equalizer comprising: a signal inputting portion, and signal withdrawing means for distributing and delaying an input signal from said signal inputting portion for withdrawing at least a main signal and first, second, third and fourth signals, said first and second signals having a time lead and a time delay, respectively, of a first predetermined time period with respect to a reference corresponding to an absolute delay amount of said main signal, and having substantially identical signal levels, said third and fourth signals having a time lead and a time delay of a second predetermined time period with respect to a reference corresponding to an absolute delay amount of said main signal, polarity inverting means for rendering said first and second signals different in polarity, first synthesizing means for synthesizing said first and second signals having said different polarities and the same signal levels, correcting signal producing means for synthesizing said third and fourth signals at substantially the same signal level for outputting an amplitude correcting signal, amplitude varying means for varying an output signal from said first synthesizing means and an output signal from said correcting signal producing means so that a predetermined amplitude ratio is obtained, means included within the equalizer for reversing a polarity of an output signal from said first synthesizing means, and second synthesizing means for synthesizing, with said main signal, an output signal from said first synthesizing means and an output signal from said correcting signal producing means having polarities which are different from each other and which have a predetermined amplitude ratio.
Claim 2
Dependent Claim
262 words
A variable group delay equalizer comprising: a signal inputting portion, and signal withdrawing means for distributing and delaying an input signal from said signal inputting portion for withdrawing at least a main signal and first, second, third and fourth signals, said first and second signals having a time lead and a time delay, respectively, of a first predetermined time period with respect to a reference corresponding to an absolute delay amount of said main signal, and having substantially identical signal levels, said third and fourth signals having a time lead and a time delay of a second predetermined time period with respect to a reference corresponding to an absolute delay amount of said main signal, polarity inverting means for rendering said first and second signals different in polarity, first synthesizing means for synthesizing said first and second signals having said different polarities and the same signal levels, correcting signal producing means for synthesizing said third and fourth signals at substantially the same signal level for outputting an amplitude correcting signal, amplitude varying means for varying an output signal from said first synthesizing means and an output signal from said correcting signal producing means so that a predetermined amplitude ratio is obtained, means included within the equalizer for reversing a polarity of an output signal from said first synthesizing means, and second synthesizing means for synthesizing, with said main signal, an output signal from said first synthesizing means and an output signal from said correcting signal producing means having polarities which are different from each other and which have a predetermined amplitude ratio.
Claim 3
Dependent Claim
47 words
A variable group delay equalizer in accordance with claim 1, wherein said correcting signal producing means comprises adder means for synthesizing said third and fourth signals of the same level, and fixed attenuator means for attenuating by a predetermined amount an output signal from said adder means.
Claim 4
Dependent Claim
29 words
A variable group delay equalizer in accordance with claims 1 or 2, wherein said second predetermined time period is selected to be two times said first predetermined time period.
Claim 5
Dependent Claim
59 words
A variable group delay equalizer in accordance with claim 3, wherein said amplitude varying means comprises amplitude adjusting means for attenuating an amplitude of an output signal from said correcting signal producing means by a factor substantially equalling a square of an amplitude attenuating factor used in attenuating an amplitude of an output signal from said first synthesizing means.
Claim 6
Dependent Claim
66 words
A variable group delay equalizer in accordance with claim 4, wherein said amplitude adjusting means comprises at least two variable attenuation setting circuits which are interposed in a signal path affecting an amplitude of an output signal from said first synthesizing means and a signal path affecting an amplitude of an output signal from said correcting signal producing means and which are ganged with each other.
Claim 7
Dependent Claim
56 words
A variable group delay equalizer in accordance with claim 5, wherein said second synthesizing means comprises a first adder for synthesizing an output signal from said first synthesizing means and an output signal from said correcting signal producing means, and a second adder for synthesizing said main signal and an output signal from said first adder.
Claim 8
Dependent Claim
58 words
A variable group delay equalizer in accordance with claim 6, wherein said amplitude adjusting means comprises a first variable attenuation setting circuit interposed between said correcting signal producing means and said first adder, and a second variable attenuation setting circuit interposed between said first adder and said second adder and ganged with said first variable attenuation setting circuit.
Claim 9
Dependent Claim
29 words
A variable group delay equalizer in accordance with claim 7, wherein said means for reversing polarity of an output signal is included in said second variable attenuation setting circuit.
Claim 10
Dependent Claim
97 words
A variable group delay equalizer in accordance with claim 6, wherein said amplitude adjusting means includes a first variable attentuation setting circuit being interposed between said first synthesizing means and said first adder, and a second variable attenuation setting circuit being interposed between said correcting signal producing means and said first adder and ganged with said first variable attenuation setting circuit, the second variable attenuation setting circuit having a coefficient of attenuation substantially equal to a square (two times in terms of a decibel scale) of a coefficient of attenuation of said first variable attenuation setting circuit.
Claim 11
Dependent Claim
29 words
A variable group delay equalizer in accordance with claim 9, wherein said means for reversing polarity of an output signal is included in the second variable attenuation setting circuit.
Claim 12
Dependent Claim
41 words
A variable group delay equalizer in accordance with claim 6, wherein said amplitude adjusting means comprises a plurality of variable attenuation setting circuits being interposed in the respective paths of said first through fourth signals and being ganged with each other.
Claim 13
Dependent Claim
47 words
A variable group delay equalizer in accordance with claim 1, wherein said signal withdrawing means comprises a distributing circuit for distributing an input signal from said signal inputting portion into at least said five signals, and delay circuit being interposed in signal paths from said distributing circuit.
Claim 14
Dependent Claim
47 words
A variable group delay equalizer in accordance with claim 12, wherein said polarity inverting means comprises at least one polarity inverter interposed between at least one of said delay circuits and said first synthesizing means, in either of said first signal path and said second signal path.
Claim 15
Dependent Claim
23 words
A variable group delay equalizer in accordance with claim 12, wherein said polarity inverting means is connected in series with said delay circuit.
Claim 16
Dependent Claim
47 words
A variable group delay equalizer in accordance with claim 1, wherein said signal withdrawing means comprises a plurality of branch circuits receiving an input signal from said signal inputting portion and connected with each other in a cascade manner, and delay circuits interposed between said branch circuits.
Claim 17
Dependent Claim
42 words
A variable group delay equalizer in accordance with claim 15, wherein said polarity inverting means is interposed between said first synthesizing means and either of the branch circuit for withdrawing said first signal and the branch circuit for withdrawing said second signal.
Claim 18
Dependent Claim
27 words
A variable group delay equalizer in accordance with claim 1, wherein said first synthesizing means and said correcting signal producing means comprise a plurality of sets, respectively.
Claim 19
Dependent Claim
92 words
An equalizer circuit for use in a communication apparatus in accordance with claim 1, which is used in a transmitting apparatus and/or a receiving apparatus and equalizes an amplitude distortion and group delay distortion caused in a transmit/receive system, and which further comprises a variable amplitude equalizer being able to vary only an amplitude frequency response characteristic in a continuous manner, and said variable group delay equalizer connected to said variable amplitude equalizer in a cascade manner and being able to vary only a group delay frequency characteristic in a continuous manner.
Claim 20
Dependent Claim
93 words
An equalizer circuit for use in communcation apparatus being used in a transmitting apparatus and/or a receiving apparatus and for equalizing an amplitude distortion and group delay distortions caused in a transmit/receive system, comprising: a variable amplitude equalizer means for varying only an amplitude frequency response characteristic substantially independently of delay and in a continuous manner, and a variable group delay equalizer means connected to said variable amplitude equalizer in a cascade manner and operable for varying only a group delay frequency response characteristic substantially independently of amplitude and in a continuous manner.
Claim 21
Dependent Claim
93 words
An equalizer circuit for use in communcation apparatus being used in a transmitting apparatus and/or a receiving apparatus and for equalizing an amplitude distortion and group delay distortions caused in a transmit/receive system, comprising: a variable amplitude equalizer means for varying only an amplitude frequency response characteristic substantially independently of delay and in a continuous manner, and a variable group delay equalizer means connected to said variable amplitude equalizer in a cascade manner and operable for varying only a group delay frequency response characteristic substantially independently of amplitude and in a continuous manner.
Claim 22
Dependent Claim
24 words
An equalizer in accordance with claim 1, wherein said signal withdrawing means comprising a signal distributor means including a plurality of hybrid circuits combined.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-01-01 | 1988-07-02 | 1989-01-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-01-01 | 1992-07-02 | 1993-01-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-01-01 | 1996-07-02 | 1997-01-01 | $7700.00 | Window Closed / Lapsed |