Control circuit for an electronically commutated motor (ECM), method of timing the electronic commutation of an ECM, and method of operating an ECM

Claim 2

In a control circuit for an electronically commutated motor adapted to be energized from a DC power source, said motor having a multistage winding assembly, and a magnetic assembly, the two arranged for mutual relative rotation, said motor in a given state of a multistate energization sequence, having an unenergized winding stage in which induced back emf appears which when integrated over time to a predetermined value indicates the instant at which the mutual relative angular position has been attained suitable for commutation to the next state, the combination comprising: solid state transconductance amplifier means adapted to be coupled to an unenergized winding stage in the motor, for converting the voltage appearing in the winding stage to a corresponding output current, integration means coupled to the output of said amplifier means for integrating said output current to obtain an output voltage substantially proportional to an integral of said voltage appearing in the winding stage; and comparison means for comparing the output voltage of said integration means to a value corresponding to the mutual relative angular position suitable for commutation, and upon sensing equality generating a timing signal at the instant for commutation.

Claim 3

The combination set forth in claim 1 wherein said transconductance amplifier means has current series feedback to stabilize amplifier transconductance.

Claim 4

In a control circuit for an electronically commutated motor adapted to be energized from a DC power source, said motor including a stator having a multistage winding arrangement with a neutral connection, and a permanent magnet rotor associated with said stator, said motor in a given stage of a multistate energization sequence, having an unenergized winding stage in which an induced back emf appears which when integrated over time to a predetermined value indicates the instant at which the rotor is at the angular position suitable for commutation to the next state, the combination comprising: a two input solid state differential transconductance amplifier means, one input adapted to be coupled to an unenergized winding stage, and the other input adapted to be coupled to a voltage equivalent to that at said neutral connection, said amplifier means converting the differential voltage appearing in the unenergized winding stage to a corresponding output current; integration means coupled to the output of said amplifier means for integrating said output current to obtain an output voltage substantially proportional to an integral of the differential voltage appearing in the winding stage; and comparison means for comparing the output voltage of said integration means to a value corresponding to the angular position of said rotor suitable for commutation, and upon sensing equality generating a timing signal at the instant for commutation.

Claim 5

In a control circuit for an electronically commutated motor adapted to be energized from a DC power source, said motor including a stator having a multistage winding arrangement with a neutral connection, and a permanent magnet rotor associated with said stator, said motor in a given stage of a multistate energization sequence, having an unenergized winding stage in which an induced back emf appears which when integrated over time to a predetermined value indicates the instant at which the rotor is at the angular position suitable for commutation to the next state, the combination comprising: a two input solid state differential transconductance amplifier means, one input adapted to be coupled to an unenergized winding stage, and the other input adapted to be coupled to a voltage equivalent to that at said neutral connection, said amplifier means converting the differential voltage appearing in the unenergized winding stage to a corresponding output current; integration means coupled to the output of said amplifier means for integrating said output current to obtain an output voltage substantially proportional to an integral of the differential voltage appearing in the winding stage; and comparison means for comparing the output voltage of said integration means to a value corresponding to the angular position of said rotor suitable for commutation, and upon sensing equality generating a timing signal at the instant for commutation.

Claim 6

The combination set forth in claim 3 wherein said transconductance amplifier means comprises a two transistor differential amplifier stage, the inputs of which are the transistor control electrodes, said stage determining the transconductance of said amplifier means, and wherein current series feedback is provided comprising a pair of resistances, one connected in series with the common electrode of one transistor of the stage and the other connected in series with the common electrode of the other transistor of said stage to stabilize said transconductance.

Claim 7

The combination set forth in claim 4 wherein said transconductance amplifier means includes at least two stages, the input stage of which is said differential amplifier; and the stage(s) succeeding said differential amplifier exhibit substantially unity current gain.

Claim 8

The combination set forth in claim 5 wherein said transconductance amplifier means further includes a first and a second solid state current mirror, the output current from the first transistor in said input stage being coupled to said first current mirror and the output current from the second transistor in said input stage being coupled to said second current mirror.

Claim 9

The combination set forth in claim 6 wherein said transconductance amplifier means includes a first and a second solid state buffer amplifier, and a third, polarity inverting, current mirror; said first buffer amplifier comprising, a third transistor having the control electrode electrically common and a first principal electrode coupled to the output of said first current mirror, and the second principal electrode coupled to the input of said polarity inverting current mirror; the second buffer amplifier comprising a fourth transistor having the control electrode electrically common and a first principal electrode coupled to the output of said second current mirror, and wherein said third current mirror comprises a fifth, output transistor having its control electrode coupled to the second principal electrode of said third transistor and a first principal electrode thereof connected to the second principal electrode of said fourth transistors, said fourth and fifth transistor being connected to provide a push-pull output in which output current is either supplied or withdrawn.

Claim 10

The combination set forth in claim 7 wherein each of said current mirrors comprises at least a first and a second solid state device, the second solid state device being a transistor, said first solid state device exhibiting a voltage drop approximately that of the input of said second device, and a first and a second resistance; a first reference series circuit, which comprises said first solid state device and said first resistance being connected in shunt with a second, mirroring series circuit, which comprises the input of said second solid state device connected in series with said second resistance.

Claim 11

The combination set forth in claim 8 and wherein the first and second resistances of said current mirrors are selected to provide significant degeneration for accuracy in the current transfer function of said mirrors.

Claim 12

The combination set forth in claim 9 wherein the transistors of said transconductance amplifier means are field effect transistors to achieve high amplifier input and output impedances.

Claim 13

In a control circuit for an electronically commutated motor adapted to be energized from a DC power source, said motor including a stator having a multistage winding arrangement with a neutral connection, and a permanent magnet rotor associated with said stator, said motor in a given state of a multistate energization sequence, having an unenergized winding stage in which an induced back emf appears which when integrated over time to a predetermined value indicates the instant at which the rotor is at the angular position suitable for commutation to the next state, the combination comprising: a two input solid state differential transconductance amplifier means, one input adapted to be coupled to an unenergized winding stage, and the other input adapted to be coupled to said neutral connection, said amplifier means converting the differential voltage appearing in the unenergized winding stage to a corresponding output current; integration means coupled to the output of said amplifier means for integrating said output current to obtain an output voltage substantially proportional to an integral of the differential voltage appearing in the winding stage; and comparison means for comparing the output voltage of said integration means to a value corresponding to the angular position of said rotor suitable for commutation, and upon sensing equality generating a timing signal at the instant for commutation.

Claim 14

In a control circuit for an electronically commutated motor adapted to be energized from a DC power source, said motor including a stator having a multistage winding arrangement with a neutral connection, and a permanent magnet rotor associated with said stator, said motor in a given state of a multistate energization sequence, having an unenergized winding stage in which an induced back emf appears which when integrated over time to a predetermined value indicates the instant at which the rotor is at the angular position suitable for commutation to the next state, the combination comprising: a two input solid state differential transconductance amplifier means, one input adapted to be coupled to an unenergized winding stage, and the other input adapted to be coupled to said neutral connection, said amplifier means converting the differential voltage appearing in the unenergized winding stage to a corresponding output current; integration means coupled to the output of said amplifier means for integrating said output current to obtain an output voltage substantially proportional to an integral of the differential voltage appearing in the winding stage; and comparison means for comparing the output voltage of said integration means to a value corresponding to the angular position of said rotor suitable for commutation, and upon sensing equality generating a timing signal at the instant for commutation.

Claim 15

The combination set forth in claim 11 wherein said transconductance amplifier means comprises a two transistor differential amplifier stage, the inputs of which are the transistor control electrodes, said stage determining the transconductance of said amplifier means, and wherein current series feedback is provided comprising a pair of resistances, one connected in series with the common electrode of one transistor of said stage and the other connected in series with the common electrode of the other transistor of said stage to stabilize said transconductance.

Claim 16

The combination set forth in claim 12 wherein said transconductance amplifier means includes at least two stages, the input stage of which is said differential amplifier, and the stage(s) succeeding said differential amplifier exhibit substantially unity current gain.

Claim 17

The combination set forth in claim 13 wherein said transconductance amplifier means further includes a first and a second solid state current mirror, the output current from the first transistor in said input stage being coupled to said first current mirror and the output current from the second transistor in said input stage being coupled to said second current mirror.

Claim 18

The combination set forth in claim 14 wherein said transconductance amplifier means further includes a first and a second solid state buffer amplifier and a third, polarity inverting, current mirror; said first buffer amplifier comprising a third transistor having the control electrode electrically common and a first principal electrode coupled to the output of said first current mirror, and the second principal electrode coupled to the input of said polarity inverting current mirror; the second buffer amplifier comprising a fourth transistor having the control electrode electrically common and a first principal electrode coupled to the output of said second current mirror, and wherein said third current mirror comprises a fifth, output transistor having its control electrode coupled to the second principal electrode of said third transistor and a first principal electrode thereof connected to the second principal electrode of said fourth transistor, said fourth and fifth transistors being connected to provide a push-pull output in which output current is either supplied or withdrawn.

Claim 19

The combination set forth in claim 15 wherein each of said current mirrors comprises at least a first and a second solid state device, the second solid state device being a transistor, said first solid stage device exhibiting a voltage drop approximating that of the input of said second device, and a first and a second resistance, a first reference series circuit, which comprises said first solid state device and said first resistance, being connected in shunt with a second, mirroring series circuit, which comprises the input of said second solid state device connected in series with said second resistance.

Claim 20

The combination set forth in claim 16 wherein the first and second resistances of said current mirrors are selected to provide significant degeneration for accuracy in the current transfer function of said mirrors.

Claim 21

The combination set forth in claim 17 wherein the transistors of said transconductance amplifier means are field effect transistors to achieve high amplifier input and output impedances.

Claim 22

The combination set forth in claim 18 wherein said transconductance amplifier means is a portion of a monolithic integrated circuit, the transistors, the current series feedback resistances, and the current mirror resistances being formed as a portion thereof, the values of said resistances exhibiting smaller variations than the values of the transconductances of said associated transistors to stabilize the transconductance of said amplifier.

Claim 23

the combination set forth in claim 3 wherein means are provided for resetting said integration means to an initial state suitable for initiating the succeeding integration, said resetting occurring after said instant for commutation, and wherein means are provided for periodically nulling the output current of said transconductance amplifier means, said nulling being timed to occur after said instant for commutation but prior to resetting said integration means.

Claim 24

The combination set forth in claim 20 wherein means are provided for sensing a null and initiating resetting of said integration means in preparation for the next commutation period.

Claim 25

The combination set forth in claim 21 wherein a low voltage DC supply is provided suitable for operation of said monolithic integrated circuit, the voltage of said supply changing at a finite rate when power to said control circuit is applied or removed; and a protection circuit producing an output responsive to the voltage of said low voltage DC supply for holding at least a portion of said control circuit in an inactive state when said voltage is below a first value when power is turned on or below a second value when power is turned off, and when said voltage has exceeded said first value as power is turned on, releasing said circuit portion at a predetermined initial state, said voltage values being set such that normal circuit operation is assured at supply voltages exceeding said values.

Claim 26

The combination set forth in claim 22 wherein said protection circuit, upon termination of said output releases said circuit portion in a state to null said amplifier means to insure balance of the output current of said amplifier means before integration.

Claim 27

In a control circuit for an electronically commutated motor adapted to be energized from a DC power source, said motor including a stator having a multistage winding arrangement with a neutral connection, and a permanent magnet rotor associated with said stator, said motor in a given state of a multistate energization sequence, having an unenergized winding stage in which an induced back emf appears which when integrated over time to a predetermined value indicates the instant at which the rotor is at the angular position suitable for commutation to the next state, the combination comprising: a two input solid state differential transconductance amplifier means, one input adapted to be coupled to an unenergized winding stage, and the other input adapted to be coupled to said neutral connection, said amplifier means converting the differential voltage appearing in the unenergized winding stage to a corresponding output current; said transconductance amplifier means comprising an input stage comprising two transistors, the control electrodes forming the inputs of said transconductance amplifier means, and a second and a third stage, the second stage being a current mirror, the output current of said first transistor being coupled to said second stage and the output current from said second transistor being coupled to said third stage; integration means coupled to the output of said amplifier means for integrating said output current to obtain an output voltage substantially proportional to an integral of the differential voltage appearing in the winding stage; and comparison means for comparing the output voltage of said integration means to a value corresponding to the angular position of said rotor suitable for commutation, and upon sensing equality generating a timing signal at the instant for commutation; means for periodically resetting said integration means to an initial state suitable for initiating the succeeding integration; and means for periodically nulling the output current of said transconductance amplifier means, said nulling being timed to occur after said instant for commutation, but prior to resetting said integration means; said nulling means comprising means for incrementing the offset current of said current mirror to a value which corrects imbalance in the output current of said transconductance amplifier means, and sustaining said corrective offset current until nulling again occurs.

Claim 28

In a control circuit for an electronically commutated motor adapted to be energized from a DC power source, said motor including a stator having a multistage winding arrangement with a neutral connection, and a permanent magnet rotor associated with said stator, said motor in a given state of a multistate energization sequence, having an unenergized winding stage in which an induced back emf appears which when integrated over time to a predetermined value indicates the instant at which the rotor is at the angular position suitable for commutation to the next state, the combination comprising: a two input solid state differential transconductance amplifier means, one input adapted to be coupled to an unenergized winding stage, and the other input adapted to be coupled to said neutral connection, said amplifier means converting the differential voltage appearing in the unenergized winding stage to a corresponding output current; said transconductance amplifier means comprising an input stage comprising two transistors, the control electrodes forming the inputs of said transconductance amplifier means, and a second and a third stage, the second stage being a current mirror, the output current of said first transistor being coupled to said second stage and the output current from said second transistor being coupled to said third stage; integration means coupled to the output of said amplifier means for integrating said output current to obtain an output voltage substantially proportional to an integral of the differential voltage appearing in the winding stage; and comparison means for comparing the output voltage of said integration means to a value corresponding to the angular position of said rotor suitable for commutation, and upon sensing equality generating a timing signal at the instant for commutation; means for periodically resetting said integration means to an initial state suitable for initiating the succeeding integration; and means for periodically nulling the output current of said transconductance amplifier means, said nulling being timed to occur after said instant for commutation, but prior to resetting said integration means; said nulling means comprising means for incrementing the offset current of said current mirror to a value which corrects imbalance in the output current of said transconductance amplifier means, and sustaining said corrective offset current until nulling again occurs.

Claim 29

The combination set forth in claim 24 wherein said nulling means comprises: means for zeroing the differential input voltage applied between said inputs of said transconductance amplifier means and for establishing a desired output current level in said first and second transistors of said input stage, amplifier output switching means for disconnecting the output of said transconductance amplifier means from said integration means during said nulling interval, and a nulling comparator coupled to the output of said transconductance amplifier for detecting a change in sense of the output current, as the amplifier goes through balance to terminate the incrementing process and initiate resetting said integration means.

Claim 30

The combination set forth in claim 25 wherein said offset current incrementing means comprises: means for supplying a clocking signal having a period which is short in relation to the commutation period, and a nulling counter counting at the rate of said clocking signal, the state of said nulling counter controlling the sum of the increments of offset current, said nulling counter being preset in response to said timing signal, wherein subsequent counting during nulling adjusts said current offset toward balance until a null is detected by said nulling comparator.

Claim 31

The combination set forth in claim 26 wherein a low voltage DC supply is provided suitable for operation of said control circuit, the voltage of said supply changing at a finite rate when power to said control circuit is turned on or turned off, and a protection circuit is provided producing an active output responsive to the voltage of said low voltage DC supply for holding at least a portion of said control circuit in an inactive state when said voltage is below a first value when power is turned on or below a second value when power is turned off, and when said voltage has exceeded said first value as power is turned on releasing said circuit portion at a predetermined initial state, said voltage values being set such that normal circuit operation is assured at supply voltages exceeding said first and second values.

Claim 32

The combination set forth in claim 27 wherein said protection circuit, upon termination of said active output as power is turned on, releases said circuit portion in a state to null said amplifier means to insure balance of the output current of said amplifier means before integration of its output current.

Claim 33

The combination set forth in claim 28 wherein said protection circuit during said active output, presets said nulling counter, and upon termination of said active output, as power is turned on releases said circuit portion in a state for nulling said amplifier means, said state for nulling comprising activation of said zeroing means at the input of said transconductance amplifier means, activation of said amplifier output switching means for disconnection, and releasing of said nulling counter.

Claim 34

The combination set forth in claim 29 wherein said protection circuit comprises means to cause a starting offset in the output current of said amplifier means to insure integration of said output current to a voltage sufficient for generation of said commutation timing signal, said starting offset current, except during said nulling interval(s) extending over a sufficient period after power is applied to allow control circuit stabilization.

Claim 35

The combination set forth in claim 30 wherein said starting offset continues after power is turned on for at least one commutation period.

Claim 36

In a control circuit for an electronically commutated motor adapted to be energized from a DC power source, said motor having a multistage winding assembly with a neutral connection, and a magnetic assembly, the two arranged for mutual relative rotation, said motor in a given state of a multistate energization sequence, having an unenergized winding stage in which an induced back emf appears which indicates the instant at which the mutual relative angular position has been attained suitable for commutation to the next state, the combination comprising: a two input solid state differential transconductance amplifier means, one input adapted to be coupled to an unenergized winding stage, and the other input adapted to be coupled to said neutral connection, said amplifier means converting the differential voltage appearing in the unenergized winding stage to a corresponding bidirectional output current in which output current is either supplied or withdrawn; integration means coupled to the output of said amplifier means for integrating said output current to obtain an output voltage substantially proportional to an integral of the differential voltage appearing in the winding stage; and comparison means for comparing the output voltage of said integration means to a value corresponding to the mutual relative angular position suitable for commutation, and upon sensing equality generating a timing signal at the instant for commutation.

Claim 37

In a control circuit for an electronically commutated motor adapted to be energized from a DC power source, said motor having a multistage winding assembly with a neutral connection, and a magnetic assembly, the two arranged for mutual relative rotation, said motor in a given state of a multistate energization sequence, having an unenergized winding stage in which an induced back emf appears which indicates the instant at which the mutual relative angular position has been attained suitable for commutation to the next state, the combination comprising: a two input solid state differential transconductance amplifier means, one input adapted to be coupled to an unenergized winding stage, and the other input adapted to be coupled to said neutral connection, said amplifier means converting the differential voltage appearing in the unenergized winding stage to a corresponding bidirectional output current in which output current is either supplied or withdrawn; integration means coupled to the output of said amplifier means for integrating said output current to obtain an output voltage substantially proportional to an integral of the differential voltage appearing in the winding stage; and comparison means for comparing the output voltage of said integration means to a value corresponding to the mutual relative angular position suitable for commutation, and upon sensing equality generating a timing signal at the instant for commutation.

Claim 38

The combination set forth in claim 32 wherein said transconductance amplifier means comprises an input stage comprising two transistors, the control electrodes forming the inputs of said transconductance amplifier means, and a second and a third stage, the second stage being a current mirror, the output current of said first transistor being coupled to said second stage and the output current from said second transistor being coupled to said third stage; and wherein means are provided for periodically resetting said integration means to an initial state suitable for initiating the succeeding integration; and means are provided for periodically nulling the output current of said transconductance amplifier means, said nulling being timed to occur after said instant for commutation, but prior to resetting said integration means; said nulling means comprising means for incrementing the offset current of said current mirror to a value which corrects imbalance in the output current of said transconductance amplifier means, and sustaining said corrective offset current until nulling again occurs.

Claim 39

The combination set forth in claim 33 wherein said nulling means comprises: means for zeroing the differential input voltage applied between said inputs of said transconductance amplifier means and for establishing a desired output current level in said first and second transistors of said input stage, amplifier output switching means for disconnecting the output of said transconductance amplifier means from said integration means during said nulling interval, and a nulling comparator coupled to the output of said transconductance amplifier for detecting a change in sense of the output current, as the amplifier goes through balance to terminate the incrementing process and initiate resetting of said integration means.

Claim 40

The combination set forth in claim 34 wherein said offset current incrementing means comprises: means for supplying a clocking signal having a period which is short in relation to the commutation period, and a nulling counter counting at the rate of said clocking signal, the state of said nulling counter controlling the sum of the increments of offset current, said nulling counter being preset in response to said timing signal, wherein subsequent counting during nulling adjusts said current offset toward balance until a null is detected by said nulling comparator.

Claim 41

The combination set forth in claim 35 wherein a low voltage DC supply is provided suitable for operation of said control circuit, the voltage of said supply changing at a finite rate when power to said control circuit is turned on or turned off, and a protection circuit is provided for producing an active output responsive to the voltage of said low voltage DC supply for holding at least a portion of said control circuit in an inactive state when said voltage is below a first value when power is turned on or below a second value when power is turned off, and when said voltage has exceeded said first value as power is turned on releasing said circuit portion at a predetermined initial state, said voltage values being set such that normal circuit operation is assured at supply voltages exceeding said first and second values.

Claim 42

The combination set forth in claim 36 wherein said protection circuit, upon termination of said active output as power is turned on, releases said circuit portion in a state to null said amplifier means to insure balance of the output current of said amplifier means before integration of its output current.

Claim 43

The combination set forth in claim 37 wherein said protection circuit during said active output, presets said nulling counter, and upon termination of said active output, as power is turned on releases said circuit portion in a state for nulling said amplifier means, said state for nulling comprising: activation of said zeroing means at the input of said transconductance amplifier means, activation of said amplifier output switching means for disconnection, and releasing of said nulling counter.

Claim 44

The combination set forth in claim 38 wherein said protection circuit comprises: means to cause a starting offset in the output current of said amplifier means to insure integration of said output current to a voltage sufficient for generation of said commutation timing signal, said starting offset current, except during said nulling interval(s), extending over a sufficient period after power is applied to allow control circuit stabilization.

Claim 45

The combination set forth in claim 39 wherein said starting offset continues after power is turned on for at least one commutation period.