US4490838A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Muting circuit for AM stereophonic receiver
Assignee: Pioneer Corp
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Filing: 1983-07-15
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Granted: 1984-12-25
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Expires: 2003-07-15
Abstract
Abstract A muting circuit for an AM stereophonic receiver of the type that having a detector circuit operating upon an AM stereophonic signal, the carrier of which is phase-modulated by the difference signal of first and second stereo channel signals, for detecting the difference signal. The muting circuit includes a muting signal generating circuit for detecting the output level of the detector circuit exceeding a predetermined value and for generating a muting signal at least for periods when the predetermined value is exceeded, and a muting switch circuit for attenuating the output of the detector in response to the muting signal.
Inventors
- 👤 Akira Nishioka
- 👤 Hitoshi Hirata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 13:31
CPC Classifications
H; H04; H04H; H04H40/00; H04H40/18; H04H40/27; H04H40/36; H03; H03G; H03G3/00; H03G3/20; H03G3/30; H03G3/34; H03G3/344; H04B; H04B1/00; H04B1/06; H04B1/10; H04B1/16; H04B1/1646; H04B1/1661
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
32 words
A sub-channel receiving circuit for an AM stereophonic receiver in which a subsignal is phase modulated onto a carrier signal, comprising; a limiter having an input coupled to receive an IF signal;
Claim 2
Dependent Claim
32 words
A sub-channel receiving circuit for an AM stereophonic receiver in which a subsignal is phase modulated onto a carrier signal, comprising; a limiter having an input coupled to receive an IF signal;
Claim 3
Dependent Claim
312 words
an FM detector having an input coupled to an output of said limiter; an integrator having an input coupled to an output of said FM detector; a first resistor having a first terminal coupled to an output of said integrator; a second resistor; a first transistor having a base coupled to a second terminal of said first resistor, a collector coupled to a supply voltage terminal, and an emitter coupled through said second resistor to ground, an L-R output signal being produced on said emitter of said first transistor; a high-pass filter having an input coupled to said output of said integrator; an amplifier having an input coupled to an output of said high-pass filter; first and second comparators, said first comparator having a positive input terminal coupled to an output of said amplifier and said second comparator having a negative input terminal coupled to said output of said amplifier; third through sixth resistors coupled in series with one another with a first terminal of said third resistor being coupled to said supply voltage terminal and a first terminal of said sixth resistor being connected to ground, a negative input of said first comparator being coupled to a junction point of said third and fourth resistors and a positive input of said second comparator being coupled to a junction point of said fifth and sixth resistors; first and second diodes having anodes coupled, respectively, to outputs of said first and second comparators, and cathodes coupled together; a seventh resistor coupled between said cathodes of said diodes and ground; a capacitor coupled in parallel with said seventh resistor; an eighth resistor; and a second transistor having a collector coupled to said base of said first transistor, an emitter coupled to a junction point of said fourth and fifth resistors and a base coupled through said eighth resistor to said cathodes of said diodes.
Claim 4
Dependent Claim
312 words
an FM detector having an input coupled to an output of said limiter; an integrator having an input coupled to an output of said FM detector; a first resistor having a first terminal coupled to an output of said integrator; a second resistor; a first transistor having a base coupled to a second terminal of said first resistor, a collector coupled to a supply voltage terminal, and an emitter coupled through said second resistor to ground, an L-R output signal being produced on said emitter of said first transistor; a high-pass filter having an input coupled to said output of said integrator; an amplifier having an input coupled to an output of said high-pass filter; first and second comparators, said first comparator having a positive input terminal coupled to an output of said amplifier and said second comparator having a negative input terminal coupled to said output of said amplifier; third through sixth resistors coupled in series with one another with a first terminal of said third resistor being coupled to said supply voltage terminal and a first terminal of said sixth resistor being connected to ground, a negative input of said first comparator being coupled to a junction point of said third and fourth resistors and a positive input of said second comparator being coupled to a junction point of said fifth and sixth resistors; first and second diodes having anodes coupled, respectively, to outputs of said first and second comparators, and cathodes coupled together; a seventh resistor coupled between said cathodes of said diodes and ground; a capacitor coupled in parallel with said seventh resistor; an eighth resistor; and a second transistor having a collector coupled to said base of said first transistor, an emitter coupled to a junction point of said fourth and fifth resistors and a base coupled through said eighth resistor to said cathodes of said diodes.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-12-25 | 1988-06-25 | 1988-12-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-12-25 | 1992-06-25 | 1992-12-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-12-25 | 1996-06-25 | 1996-12-25 | $7700.00 | Window Closed / Lapsed |