High speed multiply accumulate processor

Claim 2

Apparatus for calculating the sum of the products of pairs of numbers, each of said pairs of numbers having a first member taken from a first set of numbers and a second member taken from a second set of numbers, each of said numbers of said first set being represented by M bit binary data and each number of said second set being represented by N bit binary data, said apparatus comprising: a plurality of accumulator means, each of said accumulator means having a data port and an accumulator means select input terminating region; a first data bus adapted to carry signals representative of said first members of said pairs of numbers, said first data bus further adapted to provide said signals representative of said first members of said pairs of numbers to said data ports of said accumulator means; and a second data bus adapted to carry signals representative of said second members of said pairs of numbers, said second data bus further being adapted to provide signals representative of individual bits of said N bits of said second members of said pairs of numbers to said accumulator means select input terminating regions.

Claim 3

The apparatus of claim 1 wherein said plurality of accumulator means comprises N accumulator means.

Claim 4

The apparatus of claim 2 further comprising: a controller means having a select output terminating region and a shift output terminating region, said controller means being adapted to provide a first predetermined signal at said select output terminating region and a second predetermined signal at said shift output terminating region; an additional accumulator means having a data port, an accumulator means select input terminating region, and a shift input terminating region, additional accumulator means data port being adapted to receive signals from said first data bus, said accumulator means select input terminating region of said additional accumulator being adapted to receive said first predetermined signals from said controller means select output terminating region and said accumulator means shift input terminating region being adapted to receive said second predetermined signals from said controller means shift output terminating region, said additional accumulator means being adapted to execute a bit shift operation when said second predetermined signal is received by said accumulator means shift input terminating region.

Claim 5

The apparatus of claim 3 wherein said controller means further has a reset output terminating region adapted to provide a third predetermined signal and each of said accumulator means of said plurality thereof and said additional accumulator have a reset input terminating region adapted to receive said third predetermined signal, each of said accumulator means being adapted to have a value stored therein set equal to zero when said third predetermined signal is received at its respective accumulator means reset input terminating region.

Claim 6

The apparatus of claim 1, claim 2, claim 3, or claim 4 wherein M is equal to N.

Claim 7

The apparatus of claim 3 or claim 4 wherein said second data bus is adapted to provide each of said individual bits of said N bits to exactly one of said accumulator means select input terminating regions of said accumulator means of said plurality thereof and each of said accumulator means select input terminating regions of said accumulator means of said plurality thereof is adapted to receive exactly one bit of said N bits, each of said accumulators of said plurality thereof being adapted to be enabled when receiving a bit equal to a binary one at its respective accumulator means select input terminating region and to be disabled when receiving a bit equal to a binary zero at its respective accumulator means select input terminating region.

Claim 8

The apparatus of claim 6 wherein each of said accumulator means of said plurality thereof is adapted to calculate a sum of selected numbers of said first set of numbers and said additionl accumulator means is adapted to add said sums together, said additional accumulator means performing a bit shift operation between addition steps.

Claim 9

The apparatus of claim 7 wherein M is equal to N.