Signal processing circuit employing an improved composite current mirror circuit/device

Claim 2

An electric circuit comprising: (a) a first current mirror circuit having a first input bipolar transistor, a first coupling bipolar transistor and an output bipolar transistor, wherein the emitter of said first input transistor and the emitter of said output transistor are connected together, the base of said first input transistor and the base of said output transistor are connected together, the collector and the base of said first input transistor are connected through said first coupling transistor, a first input terminal connected to the collector of said first input transistor, and an output terminal connected to the collector of said output transistor; and (b) a second current mirror circuit having a second input bipolar transistor, a second coupling bipolar transistor, and said output transistor, wherein the emitter of said second input transistor and the emitter of said output transistor are connected together, the base of said second input transistor and the base of said output transistor are connected together, the collector and the base of said second input transistor are connected through said second coupling transistor, a second input terminal connected to the collector of said second input transistor, and an output terminal common to said output terminal of said first current mirror circuit; said first current mirror circuit further having a first additional bipolar transistor whose emitter, base and collector are respectively connected to the collector and base of said first input transistor and a reference potential, while said second current mirror circuit further has a second additional bipolar transistor whose emitter, base and a collector are respectively connected to the collector and base of said second input transistor and said reference potential; said first input terminal being supplied with a first input current and said second input terminal being supplied with a second input current, whereby an output current proportional to either greater value of the two input currents is provided from said common output terminal.

Claim 3

An electric circuit according to claim 1, wherein the base of said first input transistor and the base of said second input transistor are formed of an N-type semiconductor layer on a P-type semiconductor substrate, and the collector of said first input transistor and the collector of said second input transistor are respectively formed of a first P-type semiconductor layer and a second P-type semiconductor layer which are formed within said N-type semiconductor layer; with the result that the emitter of said first additional transistor is effectively formed of said first P-type semiconductor layer, the emitter of said second additional transistor is effectively formed of said second P-type semiconductor layer, the base of said first additional transistor and the base of said second additional transistor are effectively formed of said N-type semiconductor layer, and the collector of said first additional transistor and the collector of said second additional transistor are effectively formed of said P-type semiconductor substrate.

Claim 4

A signal processing circuit comprising: (a) a first input amplifier for amplifying a first input signal; (b) a second input amplifier for amplifying second input signal; (c) a first rectifier for producing a first rectifier current from an A.C. output signal of said first input amplifier; (d) a second rectifier for producing a second rectified current from an A.C. output signal of said second input amplifier; (e) a maximum current detector for producing an output signal which is proportional to either greater value of the first and second rectified currents; (f) a peak detector having an input terminal connected to an output terminal of said maximum current detector; (g) a time constant circuit having an input terminal connected to an output terminal of said peak detector; (h) a first variable gain amplifier circuit having an input terminal supplied with the output signal of said first input amplifier, and the gain of which is controlled by an output signal of said time constant circuit, whereby a first expanded output signal is provided from its output terminal; and (i) a second variable gain amplifier circuit having an input terminal supplied with the output signal of said second input amplifier, and the gain of which is controlled by the output signal of said time constant circuit, whereby a second expanded output signal is provided from its output terminal; and wherein said maximum current detector comprises: (1) a first current mirror circuit having a first bipolar transistor, a first coupling bipolar transistor and an output bipolar transistor, wherein the emitter of said first input transistor and the emitter of said output transistor are connected together, the base of said first input transistor and the base of said output transistor are connected together, the collector and the base of said first input transistor are connected through said first coupling transistor, a first input terminal connected to the collector of said first input transistor, and an output terminal connected to the collector of said output transistor; and (2) a second current mirror circuit having a second input bipolar transistor, a second coupling bipolar transistor and said output bipolar transistor, wherein the emitter of said second input transistor and the emitter of said output transistor are connected together, the base of said second input transistor and the base of said output transistor are connected together, the collector and the base of said second input transistor are connected through said second coupling transistor, a second input terminal connected to the collector of said second input transistor, and wherein said output terminal is connected to the collector of said output transistor; and wherein said first current mirror circuit further includes a first additional bipolar transistor whose emitter, base and collector are respectively connected to the collector and base of said first input transistor and a reference potential, while said second current mirror circuit further includes a second additional bipolar transistor whose emitter, base and collector are respectively connected to the collector and base of said second input transistor and said reference potential, and said first input terminal is supplied with said first rectified current, while said second input terminal is supplied with said second rectified current.

Claim 5

A signal processing circuit comprising: (a) a first input amplifier for amplifying a first input signal; (b) a second input amplifier for amplifying second input signal; (c) a first rectifier for producing a first rectifier current from an A.C. output signal of said first input amplifier; (d) a second rectifier for producing a second rectified current from an A.C. output signal of said second input amplifier; (e) a maximum current detector for producing an output signal which is proportional to either greater value of the first and second rectified currents; (f) a peak detector having an input terminal connected to an output terminal of said maximum current detector; (g) a time constant circuit having an input terminal connected to an output terminal of said peak detector; (h) a first variable gain amplifier circuit having an input terminal supplied with the output signal of said first input amplifier, and the gain of which is controlled by an output signal of said time constant circuit, whereby a first expanded output signal is provided from its output terminal; and (i) a second variable gain amplifier circuit having an input terminal supplied with the output signal of said second input amplifier, and the gain of which is controlled by the output signal of said time constant circuit, whereby a second expanded output signal is provided from its output terminal; and wherein said maximum current detector comprises: (1) a first current mirror circuit having a first bipolar transistor, a first coupling bipolar transistor and an output bipolar transistor, wherein the emitter of said first input transistor and the emitter of said output transistor are connected together, the base of said first input transistor and the base of said output transistor are connected together, the collector and the base of said first input transistor are connected through said first coupling transistor, a first input terminal connected to the collector of said first input transistor, and an output terminal connected to the collector of said output transistor; and (2) a second current mirror circuit having a second input bipolar transistor, a second coupling bipolar transistor and said output bipolar transistor, wherein the emitter of said second input transistor and the emitter of said output transistor are connected together, the base of said second input transistor and the base of said output transistor are connected together, the collector and the base of said second input transistor are connected through said second coupling transistor, a second input terminal connected to the collector of said second input transistor, and wherein said output terminal is connected to the collector of said output transistor; and wherein said first current mirror circuit further includes a first additional bipolar transistor whose emitter, base and collector are respectively connected to the collector and base of said first input transistor and a reference potential, while said second current mirror circuit further includes a second additional bipolar transistor whose emitter, base and collector are respectively connected to the collector and base of said second input transistor and said reference potential, and said first input terminal is supplied with said first rectified current, while said second input terminal is supplied with said second rectified current.

Claim 6

A signal processing circuit according to claim 3, wherein the base of said first input transistor and the base of said second input transistor are formed of an N-type semiconductor layer on a P-type semiconductor substrate, and the collector of said first input transistor and the collector of said second input transistor are respectively formed of a first P-type semiconductor layer and a second P-type semiconductor layer which are formed within said N-type semiconductor layer; the emitter of said first additional transistor being effectively formed of said first P-type semiconductor layer, the emitter of said second additional transistor being effectively formed of said second P-type semiconductor layer, the base of said first additional transistor and the base of said second additional transistor being effectively formed of said N-type semiconductor layer and the collector of said first additional transistor and the collector of said second additional transistor being effectively formed of said second P-type semiconductor layer, the base of said first additional transistor and the base of said second additional transistor being effectively formed of said N-type semiconductor layer, the collector of said first additional transistor and the collector of said second additional transistor being effectively formed of said P-type semiconductor substrate.

Claim 7

An electric circuit comprising: (a) a first current mirror circuit including a first input bipolar transistor, a first coupling bipolar transistor and an output bipolar transistor, the emitters of said first input and output transistors being connected together, the bases of said first input and output transistors being connected together, the base of said first input transistor being coupled through said first coupling transistor to the collector of said first input transistor, a first input terminal connected to the collector of said first input transistor to which a first input current is supplied and an output terminal coupled to the collector of said output transistor; (b) a second current mirror circuit including a second input bipolar transistor, a second coupling bipolar transistor and said output transistor, the emitters of said second input and output transistors being connected together, the bases of said second input and output transistors being connected together, the base of said second input transistor being coupled through said second coupling transistor to the collector of said second input transistor, a second input terminal connected to the collector of said second input transistor to which a second input current is supplied and an output terminal in common with the output terminal of said first current mirror circuit coupled to the collector of said output transistor; and (c) means, coupled to said first and second input transistors, for selectively preventing said first and second input transistors from being driven into their saturation states in response to an imbalance in said first and second input currents, so that an output current is coupled from said common output termnal representative of the larger of said first and second input currents.

Claim 8

An electric circuit comprising: (a) a first current mirror circuit including a first input bipolar transistor, a first coupling bipolar transistor and an output bipolar transistor, the emitters of said first input and output transistors being connected together, the bases of said first input and output transistors being connected together, the base of said first input transistor being coupled through said first coupling transistor to the collector of said first input transistor, a first input terminal connected to the collector of said first input transistor to which a first input current is supplied and an output terminal coupled to the collector of said output transistor; (b) a second current mirror circuit including a second input bipolar transistor, a second coupling bipolar transistor and said output transistor, the emitters of said second input and output transistors being connected together, the bases of said second input and output transistors being connected together, the base of said second input transistor being coupled through said second coupling transistor to the collector of said second input transistor, a second input terminal connected to the collector of said second input transistor to which a second input current is supplied and an output terminal in common with the output terminal of said first current mirror circuit coupled to the collector of said output transistor; and (c) means, coupled to said first and second input transistors, for selectively preventing said first and second input transistors from being driven into their saturation states in response to an imbalance in said first and second input currents, so that an output current is coupled from said common output termnal representative of the larger of said first and second input currents.

Claim 9

An electric circuit according to claim 5, wherein said means comprises means for selectively diverting the collector currents of said first and second input transistors so as to controllably reduce the inflow of saturation currents to said first and second input transistors.

Claim 10

An electric circuit according to claim 6, wherein said means comprises, within said first current mirror circuit a first additional bipolar transistors, the emitter, base and collector of which are respectively connected to the collector and base of said first input transistor and a reference potential terminal and, within said second current mirror circuit, a second additional bipolar transistor the emitter, base and collector of which are respectively connected to the collector and base of said second input transistor and said reference potential terminal.

Claim 11

An electric circuit according to claim 7, wherein said common output terminal is directly connected to the collector of said output transistor.

Claim 12

An electric circuit according to claim 7, wherein said first and second input and coupling transistors and said output transistor are formed as an integated circuit.

Claim 13

An electric circuit according to claim 9, wherein said first and second additional transistors are parasitic transistors within said integrated circuit.

Claim 14

An electric circuit according to claim 10, wherein the base of said first input transistor and the base of said second input transistor are formed of an N-type semiconductor layer on a P-type semiconductor substrate, and the collector of said first input transistor and the collector of said second input transistor are respectively formed of a first P-type semiconductor layer and a second P-type semiconductor layer which are formed within said N-type semiconductor layer; with the result that the emitter of said first additional transistor is effectively formed of said first P-type semiconductor layer, the emitter of said second additional transistor is effectively formed of said second P-type semiconductor layer, the base of said first additional transistor and the base of said second additional transistor are effectively formed of said N-type semiconductor layer, and the collector of said first additional transistor and the collector of said second additional transistor are effectively formed of said P-type semiconductor substrate.

Claim 15

An electric circuit according to claim 7, wherein said common output terminal is coupled through said first and second coupling transistors to the collector of said output transistor.

Claim 16

An electric circuit according to claim 8, wherein the collectors of said first and second coupling transistors are coupled to said reference potential terminal.

Claim 17

An electric circuit according to claim 8, further including first and second bias coupling transistors respectively coupled between said first and second coupling transistors and a bias voltage terminal.

Claim 18

An electric circuit according to claim 8, wherein the bases of said first and second coupling transistors are coupled to a source of bias potential.

Claim 19

An electric circuit according to claim 5, wherein said electric circuit constitutes a maximum current detector circuit within an audio signal processing circuit.

Claim 20

An electric circuit according to claim 5, wherein said electric circuit constitutes a maximum current detector circuit within a compatible expansion type expander circuit.