Automatic gain control amplifier left at an optimum gain after an end of a digital input signal

Claim 2

An automatic gain control amplifier circuit for an intermittent sequence of digital input signals, comprising variable gain amplifying means responsive to a gain control signal for amplifying each digital input signal to produce a digital output signal and control signal producing means responsive to said digital output signal for producing said gain control signal, wherein said control signal producing means comprises: first means responsive to said digital output signal for detecting presence and absence of the digital input signal in said intermittent sequence to produce a presence signal which takes a presence and an absence level when the digital input signal is present and absent in said intermittent sequence, respectively; and second means responsive to said digital output signal and said presence signal for producing said gain control signal when said presence signal takes said presence level, said second means making said gain control signal keep a specific value while said presence signal takes said absence level, said specific value being had by said gain control signal at a instant at which said presence signal is switched from said presence level to said absence level; wherein said first means comprises a signal detector responsive to said digital output signal and producing a presence signal having a presence level concurrent with a sequence of digital input signals and an absence level whenever there is no digital input signal; a clock regenerator responsive to said digital output signal for regenerating a clock sequence of clocks of the digital input signal amplified into said digital output signal; counter means responsive to said digital output signal and said presence signal for counting the clocks of said clock sequence in consideration of an amplified level taken by said digital output signal to produce a count signal when said presence signal takes said presence level, said counter means holding a specific count while said presence signal takes said absence level, said specific count being a count to which the clocks of said clock sequence are counted when said presence signal is switched from said presence level to said absence level; and means responsive to said count signal for producing said gain control signal.

Claim 3

An automatic gain control amplifier circuit as claimed in claim 1, wherein said counter means comprises: a level comparator for comparing said amplified level with a reference level to produce a comparison result signal which takes a first and a second level when said amplified level is higher and lower than said reference level, respectively; an AND circuit enabled to allow the clocks of said clocks sequence to pass therethrough only when said presence signal takes said presence level; and an up-down counter preset to a predetermined count upon energization of a power source for said automatic gain control amplifier circuit and capable of counting the clocks supplied through said AND circuit up and down from said predetermined count when said comparison result signal takes a predetermined one and the other of said first and said second levels, respectively, said up-down counter thereby making said count signal represent a count to which the clocks of said clock sequence are counted from time to time, said up-down counter holding, as said specific count, the count to which the clocks of said clock sequence are counted at the instant at which said presence signal is switched from said presence level to said absence level.

Claim 4

An automatic gain control amplifier circuit as claimed in claim 2 said gain control signal being for controlling said amplified level to an optimum level predetermined in common for the digital output signals into which the respective digital input signals of said intermittent sequence are amplified, wherein said reference level is rendered substantially equal to said optimum level.

Claim 5

An automatic gain control amplifier circuit for an intermittent sequence of digital input signals, comprising variable gain amplifying means responsive to a gain control signal for amplifying each digital input signal to produce a digital output signal and control signal producing means responsive to said digital output signal for producing said gain control signal, wherein said control signal producing means comprises: first means responsive to said digital output signal for detecting presence and absence of the digital input signal in said intermittent sequence to produce a presence signal which takes a presence and an absence level when the digital input signal is present and absent in said intermittent sequence, respectively; and second means responsive to said digital output signal and said presence signal for producing said gain control signal when said presence signal takes said presence level, said second means making said gain control signal keep a specific value while said presence signal takes said absence level, said specific value being had by said gain control signal at an instant at which said presence signal is switched from said presence level to said absence level; wherein said second means comprises; a clock regenerator responsive to said digital output signal for regenerating a clock sequence of clocks of the digital input signal amplified into said digital output signal; counter means responsive to said digital output signal and said presence signal for counting the clocks of said clock sequence in consideration of an amplified level taken by said digital output signal to produce a count signal when said presence signal takes said presence level, said counter means holding a specific count while said presence signal takes said absence level, said specific count being a count to which the clocks of said clock sequence are counted when said presence signal is switched from said presence level to said absence level; and means responsive to said count signal for producing said gain control signal; and wherein said counter means comprises; a level comparator for comparing said amplified level with a reference level to produce a comparison result signal which takes a first and a second level when said amplified level is higher and lower than said reference level, respectively; an AND circuit enabled to allow the clocks of said clock sequence to pass therethrough only when said preence signal takes said presence level; and an up-down counter preset to a predetermined count upon energization of a power source for said automatic gain control amplifier circuit and capable of counting the clocks supplied through said AND circuit up and down from said predetermined count when said comparison result signal takes a predetermined one and the other of said first and said second levels, respectively, said up-down counter thereby making said count signal represent a count to which the clocks of said clock sequence are counted from time to time, said up-down counter holding, as said specific count, the count to which the clocks of said clock sequence are counted at the instant at which said presence signal is switched from said presence level to said absence level.

Claim 6

An automatic gain control amplifier circuit for an intermittent sequence of digital input signals, comprising variable gain amplifying means responsive to a gain control signal for amplifying each digital input signal to produce a digital output signal and control signal producing means responsive to said digital output signal for producing said gain control signal, wherein said control signal producing means comprises: first means responsive to said digital output signal for detecting presence and absence of the digital input signal in said intermittent sequence to produce a presence signal which takes a presence and an absence level when the digital input signal is present and absent in said intermittent sequence, respectively; and second means responsive to said digital output signal and said presence signal for producing said gain control signal when said presence signal takes said presence level, said second means making said gain control signal keep a specific value while said presence signal takes said absence level, said specific value being had by said gain control signal at an instant at which said presence signal is switched from said presence level to said absence level; wherein said second means comprises; a clock regenerator responsive to said digital output signal for regenerating a clock sequence of clocks of the digital input signal amplified into said digital output signal; counter means responsive to said digital output signal and said presence signal for counting the clocks of said clock sequence in consideration of an amplified level taken by said digital output signal to produce a count signal when said presence signal takes said presence level, said counter means holding a specific count while said presence signal takes said absence level, said specific count being a count to which the clocks of said clock sequence are counted when said presence signal is switched from said presence level to said absence level; and means responsive to said count signal for producing said gain control signal; and wherein said counter means comprises; a level comparator for comparing said amplified level with a reference level to produce a comparison result signal which takes a first and a second level when said amplified level is higher and lower than said reference level, respectively; an AND circuit enabled to allow the clocks of said clock sequence to pass therethrough only when said preence signal takes said presence level; and an up-down counter preset to a predetermined count upon energization of a power source for said automatic gain control amplifier circuit and capable of counting the clocks supplied through said AND circuit up and down from said predetermined count when said comparison result signal takes a predetermined one and the other of said first and said second levels, respectively, said up-down counter thereby making said count signal represent a count to which the clocks of said clock sequence are counted from time to time, said up-down counter holding, as said specific count, the count to which the clocks of said clock sequence are counted at the instant at which said presence signal is switched from said presence level to said absence level.

Claim 7

An automatic gain control amplifier circuit as claimed in claim 4, said gain control signal being for controlling said amplified level to an optimum level predetermined in common for the digital output signals into which the respective digital input signals of said intermittent sequence are amplified, wherein said reference level is rendered substantially equal to said optimum level.