US4488263A
Expired / Lapsed
US
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Bypass circuit for word line cell discharge current
Assignee: National Semiconductor Corp
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Filing: 1982-03-29
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Granted: 1984-12-11
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Expires: 2002-03-29
Abstract
Abstract A current bypass for a microelectric memory, such as a static RAM, diverts word line discharge current such that the current does not flow through the memory cells of a selected word line or along an upper word line conductor. In a first embodiment, the bypass comprises a resistor R1 (R2) and a diode D10 (D20) in series and coupled between an upper word line conductor 50 and word line discharge current source V CC , and a lower word line conductor 51 and word line discharge current sink 42. In another embodiment of the invention, a transistor Q10 (Q20) is used in lieu of the diode. By bypassing current from the upper word line conductor and word line memory cells, metal migration is eliminated and narrower metal lines may be used to form the word lines. By eliminating a flow of steady state discharge current through the memory cells, memory cell current saturation is eliminated.
Inventors
- 👤 William H. Herndon
- 👤 Jonathan J. Stinehelfer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 02:00
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/414; G11C11/415
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
77 words
In a semiconductor memory, a bypass circuit for diverting a flow of word line discharge current from memory cells of a selected word line and from an upper word line conductor to a word line discharge current sink, comprising: a resistor having a first terminal connected to said upper word line conductor; and a diode connected in series with said resistor, said diode being connected between a second resistor terminal and said word line discharge current sink.
Claim 2
Dependent Claim
77 words
In a semiconductor memory, a bypass circuit for diverting a flow of word line discharge current from memory cells of a selected word line and from an upper word line conductor to a word line discharge current sink, comprising: a resistor having a first terminal connected to said upper word line conductor; and a diode connected in series with said resistor, said diode being connected between a second resistor terminal and said word line discharge current sink.
Claim 3
Dependent Claim
25 words
The bypass circuit of claim 1, further comprising a second diode connected between a lower word line conductor and said word line discharge current sink.
Claim 4
Dependent Claim
15 words
The bypass circuit of claim 1, wherein said microelectronic memory is a random access memory.
Claim 5
Dependent Claim
168 words
In a semiconductor memory including a matrix of memory cells arranged in a plurality of word lines, the cells in each word line connected between an upper word line conductor and a lower word line conductor, said word lines being sequentially selectable by operation of a word line driver located at one end of each selected word line, the improvement comprising: a resistor in each word line having a first terminal connected to said upper word line conductor, said resistor being located on the word line driver's end of said word line; and a diode in each word line connected in series with said resistor, said diode being connected between a second resistor terminal and a word line discharge current sink, said diode being located on the word line driver's end of the word line, wherein a flow of word line discharge current is diverted from said memory cells and from said upper word line conductor of a selected word line to said word line discharge current sink.
Claim 6
Dependent Claim
168 words
In a semiconductor memory including a matrix of memory cells arranged in a plurality of word lines, the cells in each word line connected between an upper word line conductor and a lower word line conductor, said word lines being sequentially selectable by operation of a word line driver located at one end of each selected word line, the improvement comprising: a resistor in each word line having a first terminal connected to said upper word line conductor, said resistor being located on the word line driver's end of said word line; and a diode in each word line connected in series with said resistor, said diode being connected between a second resistor terminal and a word line discharge current sink, said diode being located on the word line driver's end of the word line, wherein a flow of word line discharge current is diverted from said memory cells and from said upper word line conductor of a selected word line to said word line discharge current sink.
Claim 7
Dependent Claim
40 words
The improvement of claim 4, further comprising a second diode connected between said lower word line conductor and said word line discharge current sink, said second diode being located on the said word line driver's end of the word line.
Claim 8
Dependent Claim
14 words
The improvement of claim 4, wherein the microelectronic memory is a random access memory.
Claim 9
Dependent Claim
98 words
In a semiconductor memory, a bypass for diverting a flow of word line discharge current from cells of a selected word line and from an upper word line to a word line discharge current sink, comprising: a transistor having a base, an emitter, and a collector, the base of said transistor being connected to said upper word line conductor, the collector of said transistor being connected to a word line discharge current source; and a resistor having a first terminal connected to said transistor's emitter and having a second terminal connected to a word line discharge current sink.
Claim 10
Dependent Claim
98 words
In a semiconductor memory, a bypass for diverting a flow of word line discharge current from cells of a selected word line and from an upper word line to a word line discharge current sink, comprising: a transistor having a base, an emitter, and a collector, the base of said transistor being connected to said upper word line conductor, the collector of said transistor being connected to a word line discharge current source; and a resistor having a first terminal connected to said transistor's emitter and having a second terminal connected to a word line discharge current sink.
Claim 11
Dependent Claim
24 words
The bypass circuit of claim 7, further comprising a diode coupled between a lower word line conductor and said word line discharge current sink.
Claim 12
Dependent Claim
15 words
The bypass circuit of claim 7, wherein the microelectronic memory comprises a random access memory.
Claim 13
Dependent Claim
171 words
In a semiconductor memory including a matrix of memory cells arranged in a plurality of word lines, the cells in each word line connected between an upper word line conductor and a lower word line conductor, said word lines being sequentially selectable by operation of a word line driver located at one end of each selected word line, the improvement comprising: a transistor having a base, an emitter, and a collector, the base of said transistor being connected to said upper word line conductor, the collector of said transistor being connected to a word line discharge current source; a resistor having a first terminal connected to said transistor's emitter and having a second terminal connected to a word line discharge current sink; the transistor and resistor being located on the word line driver's end of the word line, wherein a flow of word line discharge current is diverted from said memory cells and from said upper word line conductor of a selected word line to said word line discharge current sink.
Claim 14
Dependent Claim
171 words
In a semiconductor memory including a matrix of memory cells arranged in a plurality of word lines, the cells in each word line connected between an upper word line conductor and a lower word line conductor, said word lines being sequentially selectable by operation of a word line driver located at one end of each selected word line, the improvement comprising: a transistor having a base, an emitter, and a collector, the base of said transistor being connected to said upper word line conductor, the collector of said transistor being connected to a word line discharge current source; a resistor having a first terminal connected to said transistor's emitter and having a second terminal connected to a word line discharge current sink; the transistor and resistor being located on the word line driver's end of the word line, wherein a flow of word line discharge current is diverted from said memory cells and from said upper word line conductor of a selected word line to said word line discharge current sink.
Claim 15
Dependent Claim
39 words
The improvement of claim 10, further comprising a second diode connected between the lower word line conductor and the word line discharge current sink, said second diode being located on the word line driver's end of the word line.
Claim 16
Dependent Claim
14 words
The improvement of claim 10 wherein the microelectronic memory is a random access memory.
Claim 17
Dependent Claim
47 words
In a microelectronic memory, a method for reducing metal migration along upper word line conductors and for reducing memory cell saturation, comprising bypassing a flow of word line discharge current from a word line driver, through a series-connected resistor and diode, to a word line discharge sink.
Claim 18
Dependent Claim
47 words
In a microelectronic memory, a method for reducing metal migration along upper word line conductors and for reducing memory cell saturation, comprising bypassing a flow of word line discharge current from a word line driver, through a series-connected resistor and diode, to a word line discharge sink.
Claim 19
Dependent Claim
53 words
In a microelectronic memory, a method for reducing metal migration along upper word line conductors and for reducing memory cell saturation, comprising bypassing a flow of word line discharge current from a word line driver, through a transistor having a resistor in series with its emitter, to a word line discharge current sink.
Claim 20
Dependent Claim
53 words
In a microelectronic memory, a method for reducing metal migration along upper word line conductors and for reducing memory cell saturation, comprising bypassing a flow of word line discharge current from a word line driver, through a transistor having a resistor in series with its emitter, to a word line discharge current sink.
References Cited (Backward Citations)
US4349895A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-12-11 | 1988-06-11 | 1988-12-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-12-11 | 1992-06-11 | 1992-12-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-12-11 | 1996-06-11 | 1996-12-11 | $7700.00 | Window Closed / Lapsed |