Two dimensional press brake control system and apparatus

Claim 2

A press brake controller for producing a control signal to control the travel of the ram of a press brake, said controller including: means for providing a specified ram position signal corresponding to a predetermined bend parameter; a ram encoder connected to said ram for providing an actual ram position signal; a ram signal comparator forming a ram error signal corresponding to the difference between said ram location signal and said ram position signal; and a ram signal compensator forming said control signal corresponding to the averaged sum of said ram position signal and said ram error signal.

Claim 3

The press brake controller of claim 1 for performing a sequence of bends, said controller further comprising: means for providing a sequence of ram position signals each corresponding to each of said bend; and a step increment means connected to increment said means for providing a sequence of ram position signals to provide the next said ram position signal.

Claim 4

The press brake controller of claim 2 further including: means to display said position dimension value; and means to receive prerecorded position dimension value.

Claim 5

A press brake controller for producing a control signal to control the ram of a press brake, said press brake controller enabling said press brake to repetitively perform a bend having a predetermined dimension value corresponding to a bend angle, each bend being initiated according to a ram control switch, said controller including: means for providing an averaged ram position signal corresponding to said predetermined dimension value; a ram encoder connected to said ram providing a ram location signal; a ram signal comparator forming a ram error signal corresponding to the difference between each said location signal and said ram position signal; a ram error averager receiving said ram error signal and forming a ram average error signal corresponding to the average of a plurality of each said ram error signals, said plurality of ram error signals including ram error signals from a prior bend; and a ram signal compensator forming a control signal corresponding to the sum of said ram position signal and said ram average error signal.

Claim 6

A press brake controller for producing a control signal to control the ram of a press brake, said press brake controller enabling said press brake to repetitively perform a bend having a predetermined dimension value corresponding to a bend angle, each bend being initiated according to a ram control switch, said controller including: means for providing an averaged ram position signal corresponding to said predetermined dimension value; a ram encoder connected to said ram providing a ram location signal; a ram signal comparator forming a ram error signal corresponding to the difference between each said location signal and said ram position signal; a ram error averager receiving said ram error signal and forming a ram average error signal corresponding to the average of a plurality of each said ram error signals, said plurality of ram error signals including ram error signals from a prior bend; and a ram signal compensator forming a control signal corresponding to the sum of said ram position signal and said ram average error signal.

Claim 7

The press brake control system of claims 1 or 4 further including safety alarm means comprising alarm position measurement means connected to said ram for producing an alarm position signal corresponding to said ram position; absolute position limit detection means for providing an alarm output signal when said alarm position signal exceeds a predetermined absolute position; and adjustable position limit detection means for providing an alarm output signal when said alarm position signal exceeds a predetermined adjustable ram position signal; wherein said safety alarm means is independently operable from said ram signal comparator.

Claim 8

Means for data communication between a first processor system and a second processor system comprising: a communication channel interconnecting said first and second processor systems; message transmission means within said first processor system for providing a message signal to said transmission channel; message echo means within said second processor system for subsequently retransmitting said message signal on said transmission channel from the received said message signal; means to compare the message signal retransmitted by the second processor system with the message signal transmitted by the first processor system; message verify means within said first processor system for subsequently providing a verify signal on said communication channel upon correct receipt of said message signal after retransmission on said transmission line; verify echo means within said second processor system for subsequently retransmitting said verify signal on said communication channel as received by said verify echo means; and means to indicate the equality of the message and the message echo signals, and the message verify and the echo verify signals.

Claim 9

Means for data communication between a first processor system and a second processor system comprising: a communication channel interconnecting said first and second processor systems; message transmission means within said first processor system for providing a message signal to said transmission channel; message echo means within said second processor system for subsequently retransmitting said message signal on said transmission channel from the received said message signal; means to compare the message signal retransmitted by the second processor system with the message signal transmitted by the first processor system; message verify means within said first processor system for subsequently providing a verify signal on said communication channel upon correct receipt of said message signal after retransmission on said transmission line; verify echo means within said second processor system for subsequently retransmitting said verify signal on said communication channel as received by said verify echo means; and means to indicate the equality of the message and the message echo signals, and the message verify and the echo verify signals.

Claim 10

The means of claim 6 further comprising: channel request means within said first processor system for providing a channel request signal to said communication channel; channel acknowledgement transmission means within said second processor system for providing an acknowledgement signal to said communication channel after receipt of said channel request signal; and channel acknowledgement receiver means within said first system to enable said message transmission means to provide said message signal after receipt of said acknowledgement signal.

Claim 11

The means of claim 6, wherein said communication channel is a serial communication channel.

Claim 12

The means of claim 8, wherein said serial communication channel is operable in accordance with RS-232 signal format standards.

Claim 15

The method of claim 10 further comprising the steps of: requesting the data communications channel by said first processor; and acknowledging the request for said channel by sending an acknowledge signal from said second processor to said first processor, wherein the receipt of said acknowledge signal enables said first processor to initiate the step of sending a message signal.

Claim 16

The method of claim 10, including the steps of: detecting an interference condition when a non-recognizable signal is received by both said first processor and said second processor; sending from said first processor a status check signal, to be received by said second processor; and acknowledging said status check signal by transmitting an acknowledge signal from said second processor to said first processor, wherein the receipt of said acknowledge signal triggers the transmission of either an idle signal or a message signal from the first processor to the second processor.

Claim 17

The method of claim 12 wherein the first processor transmitted an idle signal, further including the steps of: sending an idle signal from said second processor to said first processor following receipt of said idle signal.

Claim 18

The method of claim 12 wherein the first processor transmitted an idle signal, further including the step of: sending a message signal from said second processor to said first processor following receipt of said idle signal.

Claim 19

A digital multiplier receiving sine and cosine incremented encoders signals, each said sine and cosine signal having a periodicity, said multiplier comprising: direction detection means for producing a direction output signal; transition detection means for receiving said sine and cosine signals producing a rate output signal having a periodicity at a multiple of said sine and cosine signal periodicity; clock means for providing periodic clock pulses; and inhibit means for detecting a first transition of said sine and cosine signals after said clock pulse, wherein said inhibit means operates for inhibiting said transition detection when said sine and cosine signals make a transition before the subsequent clock pulse.

Claim 20

A digital multiplier receiving sine and cosine incremented encoders signals, each said sine and cosine signal having a periodicity, said multiplier comprising: direction detection means for producing a direction output signal; transition detection means for receiving said sine and cosine signals producing a rate output signal having a periodicity at a multiple of said sine and cosine signal periodicity; clock means for providing periodic clock pulses; and inhibit means for detecting a first transition of said sine and cosine signals after said clock pulse, wherein said inhibit means operates for inhibiting said transition detection when said sine and cosine signals make a transition before the subsequent clock pulse.

Claim 21

A digital multiplier receiving sine and cosine incremental encoders signals, each said sine and cosine signal having a periodicity, said multiplier comprising: direction detection means for receiving said sine and cosine signals and for producing a direction output; transition detection means for receiving said sine and cosine signals and for producing a rate output signal having a periodicity at a multiple of said sine and cosine signal periodicity; clock means for providing periodic clock pulses; and inhibit means to inhibit said rate output signal when transitions from a first state to a second state to said first state occur within one of said clock periods.

Claim 22

A digital multiplier receiving sine and cosine incremental encoders signals, each said sine and cosine signal having a periodicity, said multiplier comprising: direction detection means for receiving said sine and cosine signals and for producing a direction output; transition detection means for receiving said sine and cosine signals and for producing a rate output signal having a periodicity at a multiple of said sine and cosine signal periodicity; clock means for providing periodic clock pulses; and inhibit means to inhibit said rate output signal when transitions from a first state to a second state to said first state occur within one of said clock periods.

Claim 23

The digital multiplier of claims 15 or 16 wherein the rate output signal of said transition detection means has a duration of one clock period.

Claim 24

The digital multiplier of claim 17 wherein said transition detection means comprises: first positive differentation means for receiving the sine signal to produce an output signal after a rising pulse edge of the sine signal; first negative differentiation means for receiving the sine signal to produce an output signal after a falling edge of the sine signal; second positive differentiation means for receiving the cosine signal to produce an output signal after a rising edge of the cosine input; and second negative differentiation means for receiving the cosine signal to produce an output signal after a falling edge of the cosine signal; wherein said first positive and negative differentiation means are interconnected and said second positive and negative differentiation means are interconnected to inhibit one of the respective positive and negative differentiation means until the other of said positive and negative differentation means has completed its output signal.

Claim 25

A press brake controller for producing a control signal to control the travel of the ram of a press brake, said controller including: means for providing a specified ram position signal corresponding to a predetermined bend parameter; a ram encoder connected to said ram providing an actual ram position signal; a ram signal comparator forming a ram error signal corresponding to the difference between said ram location signal and said ram position signal; and a ram signal compensator forming said control signal corresponding to the averaged sum of said ram position signal and said ram error signal, wherein said ram encoder comprises: incremental encoder means connected to the press brake for providing sine and cosine pulse output pulse signals each having a pulse rate corresponding to the velocity of the attached press brake element motions; digital multiplier means including: direction detection means for producing a direction output; transition detection means for receiving said sine and cosine output signals and for producing a rate output at a multiple of said incremental encoder pulse rate; clock means for providing periodic clock pulses; and inhibit means for inhibiting said transition detection means rate output signal transition when one of said sine and cosine input signals has a duration of less than one clock pulse period, wherein said direction output and said rate output taken together form said ram position signal.

Claim 26

A press brake controller for producing a control signal to control the travel of the ram of a press brake, said controller including: means for providing a specified ram position signal corresponding to a predetermined bend parameter; a ram encoder connected to said ram providing an actual ram position signal; a ram signal comparator forming a ram error signal corresponding to the difference between said ram location signal and said ram position signal; and a ram signal compensator forming said control signal corresponding to the averaged sum of said ram position signal and said ram error signal, wherein said ram encoder comprises: incremental encoder means connected to the press brake for providing sine and cosine pulse output pulse signals each having a pulse rate corresponding to the velocity of the attached press brake element motions; digital multiplier means including: direction detection means for producing a direction output; transition detection means for receiving said sine and cosine output signals and for producing a rate output at a multiple of said incremental encoder pulse rate; clock means for providing periodic clock pulses; and inhibit means for inhibiting said transition detection means rate output signal transition when one of said sine and cosine input signals has a duration of less than one clock pulse period, wherein said direction output and said rate output taken together form said ram position signal.

Claim 27

The press brake controller of claim 19, wherein the controller further comprises: a first processor receiving at least one of said direction output and said rate output; a second processor; and data communication means connected to transmit data between said first processor and said second processor.

Claim 28

The press brake controller of claim 20, wherein said data communication means comprises: a communication channel interconnecting said first and said second processors, and said controller further comprising: message transmission means within said first processor for providing a message signal to said transmission channel; message echo means within said second processor for subsequently providing a message echo signal on said communication channel from the received said message signal; signal comparison means for receiving a message signal and an echo signal, and for providing an output signal when identical; message verify means within said first processor system for subsequently providing a verify signal on said communication channel upon output of said signal comparison means; verify echo means within said second processor system for subsequently retransmitting said verify signal on said communication channel; and means to indicate the equality of the verify signals and verify echo signals.

Claim 29

The press brake control system of claim 21 wherein the first processor is a display unit and the second processor is a main control unit.

Claim 30

The press brake control system of claim 22 wherein a ram control signal is produced to produce a corresponding punch excursion distance for a predetermined bend angle determined by calculating the following equation: d=(Rd+Rp+t)(1-cos α)+[w/2-(Rd+Rp+t) sin α] tan α where d is the punch excursion distance, cos α is the cosine of the tilt angle, sin α is the sine of the tilt angle, Rd is the die corner radius, Rp is the punch nose radius, t is the material thickness, and w is the die width between the die corner radii.

Claim 31

The press brake control system of claim 23 wherein the ram control signal includes a springback correction signal determined by calculating the following equation: Δα=α'K/(1-K) where K is a variable determined by calculating the equation ##EQU4## and where σ is the yield strength, γ is Poisson's ratio, α' is the tilt angle after springback, E is the elastic modulus, and Δα is the springback correction.

Claim 32

A press brake controller for producing a control signal to control the ram of a press brake, said press brake controller enabling said press brake to repetitively perform a bend having a predetermined dimension value corresponding to a bend angle, each bend being initiated according to a ram control switch, said controller including: a ram position specifier providing an averaged ram position signal corresponding to said predetermined dimension value; a ram encoder connected to said ram providing a ram location signal; a ram signal comparator forming a ram error signal corresponding to the difference between each said location signal and said ram position signal; a ram error averager receiving said ram error signal and forming a ram average error signal corresponding to the average of a plurality of each said ram error signals, said plurality of ram error signals including ram error signals from a prior bend; and a ram signal compensator forming a control signal corresponding to the sum of said ram position signal and said ram average error signal, wherein said ram encoder comprises: incremental encoder means connected to the press brake providing sine and cosine pulse output pulse signals each having a pulse rate corresponding to the velocity of the attached press brake element motions; digital multiplier means including: direction detection means producing a direction output;

Claim 33

A press brake controller for producing a control signal to control the ram of a press brake, said press brake controller enabling said press brake to repetitively perform a bend having a predetermined dimension value corresponding to a bend angle, each bend being initiated according to a ram control switch, said controller including: a ram position specifier providing an averaged ram position signal corresponding to said predetermined dimension value; a ram encoder connected to said ram providing a ram location signal; a ram signal comparator forming a ram error signal corresponding to the difference between each said location signal and said ram position signal; a ram error averager receiving said ram error signal and forming a ram average error signal corresponding to the average of a plurality of each said ram error signals, said plurality of ram error signals including ram error signals from a prior bend; and a ram signal compensator forming a control signal corresponding to the sum of said ram position signal and said ram average error signal, wherein said ram encoder comprises: incremental encoder means connected to the press brake providing sine and cosine pulse output pulse signals each having a pulse rate corresponding to the velocity of the attached press brake element motions; digital multiplier means including: direction detection means producing a direction output;

Claim 34

transition detection means receiving said sine and cosine output signal producing a rate output at a multiple of said incremental encoder pulse rate; clock means providing periodic clock pulses; and inhibit means to inhibit said transition detection means rate output signal transition when one of said sine and cosine input signals has a duration of less than one clock pulse period, wherein said direction output and said transition rate output taken together form said ram position signal.

Claim 35

transition detection means receiving said sine and cosine output signal producing a rate output at a multiple of said incremental encoder pulse rate; clock means providing periodic clock pulses; and inhibit means to inhibit said transition detection means rate output signal transition when one of said sine and cosine input signals has a duration of less than one clock pulse period, wherein said direction output and said transition rate output taken together form said ram position signal.