Process for forming and locating buried layers

Claim 1

A method for marking an integrated circuit to facilitate mask alignment, said method comprising the following steps: (a) forming a silicon dioxide layer on the substrate; (b) etching a predetermined pattern in said silicon dioxide layer, said pattern including one or more alignment mark holes formed over inactive regions of the substrate; (c) stopping the etch of step (b) prior to exposing the underlying substrate; (d) depositing a photoresist layer over the silicon dioxide layer to fill in the pattern formed in step (b); (e) exposing and developing the photoresist layer to remove photoresist from the alignment mark holes only; and (f) etching the substrate to remove the remaining silicon dioxide from the alignment mark hole and to further form a recess in the substrate, whereby the recess may be used for alignment of active regions in subsequently deposited layers while the remainder of the substrate surface is substantially flat.

Claim 2

A method for marking an integrated circuit to facilitate mask alignment, said method comprising the following steps: (a) forming a silicon dioxide layer on the substrate; (b) etching a predetermined pattern in said silicon dioxide layer, said pattern including one or more alignment mark holes formed over inactive regions of the substrate; (c) stopping the etch of step (b) prior to exposing the underlying substrate; (d) depositing a photoresist layer over the silicon dioxide layer to fill in the pattern formed in step (b); (e) exposing and developing the photoresist layer to remove photoresist from the alignment mark holes only; and (f) etching the substrate to remove the remaining silicon dioxide from the alignment mark hole and to further form a recess in the substrate, whereby the recess may be used for alignment of active regions in subsequently deposited layers while the remainder of the substrate surface is substantially flat.

Claim 6

A method for forming vertically spaced apart regions on an integrated circuit substrate, said method comprising the following steps: (a) forming a recess in an inactive region of the substrate, said recess defining an alignment mark; (b) forming an array of doped regions located in a predefined pattern relative to the alignment mark, wherein steps (a) and (b) are performed in a predetermined order under conditions which leave the surface of the substrate other than the alignment mark substantially flat; (c) depositing an epitaxial layer over the substrate whereby the surface of the epitaxial layer is substantially flat except for the alignment mark; and (d) forming an array of doped regions on the epitaxial layer, where the location of the array is determined by reference to the alignment mark.

Claim 7

A method for forming vertically spaced apart regions on an integrated circuit substrate, said method comprising the following steps: (a) forming a recess in an inactive region of the substrate, said recess defining an alignment mark; (b) forming an array of doped regions located in a predefined pattern relative to the alignment mark, wherein steps (a) and (b) are performed in a predetermined order under conditions which leave the surface of the substrate other than the alignment mark substantially flat; (c) depositing an epitaxial layer over the substrate whereby the surface of the epitaxial layer is substantially flat except for the alignment mark; and (d) forming an array of doped regions on the epitaxial layer, where the location of the array is determined by reference to the alignment mark.