Defect detecting apparatus and method

Claim 2

Defect detecting apparatus for detecting a defect in a substrate including a defect at the periphery thereof, said substrate being sequentially scanned by an image pickup device along each of a plurality of vertically displaced horizontal lines for equal horizontal scanning periods, comprising: binary coder means coupled to the output of said image pickup device, said binary coder means converting the output of said image pickup device to a binary coded signal having a polarity determined by the amount of light reflected from said substrate at each incremental portion of said scanning periods; signal shifting means for shifting said binary coded signal for a first interval which is less than said horizontal scanning period to obtain a first shifted output; further signal shifting means for shifting said coded binary signal for a second interval, measured from the end of said first interval, which is equal to said horizontal scanning period to obtain a second shifted output; and comparator means for comparing the polarities of said first and second shifted outputs, the presence of a defect in said substrate being indicated when said first and second shifted outputs have predetermined opposite polarities at a given instant of time followed by a reversal in the polarities of each of said first and second shifted outputs.

Claim 3

Defect detecting apparatus for detecting a defect in a substrate including a defect at the periphery thereof, said substrate being sequentially scanned by an image pickup device along each of a plurality of vertically displaced horizontal lines for equal horizontal scanning periods, comprising: a binary coder coupled to the output of said image pickup device, said binary coder converting the output of said image pickup device to a binary coded signal having a polarity determined by the amount of light reflected from said substrate at each incremental portion of said scanning periods; a first shift register having an input coupled to the output of said binary coder and at least first and second outputs, the signal at said first output being delayed with respect to the signal at the input of said first shift register for an interval equal to said horizontal scanning period and the signal at said second output being delayed with respect to the signal at the input of said first shift register for a fixed interval less than said horizontal scanning period; a second shift register having an input coupled to the first output of said first shift register and at least a first output, the signal at the first output of said second shift register being delayed with respect to the signal at the input of said second shift register for a fixed interval equal to the fixed interval by which the second output of said first shift register is delayed with respect to the input of said first shift register; a first comparator having at least first and second inputs coupled to the first output of said second shift register and the second output of said first shift register respectively, said first comparator generating a signal at the output thereof when the signals at its first and second inputs are of predetermined opposite polarities; and a second comparator having at least first and second inputs coupled to the first output of said second shift register and to the second output of said first shift register respectively, said second comparator further having a third input coupled to the output of said first comparator, said second comparator generating a signal at the output thereof after generation of a signal at the output of said first comparator and when the signals at its first and second inputs are of polarities opposite the polarities of the first and second inputs respectively of said first comparator which caused generation of the output signal of said first comparator, generation of a signal at the output of said second comparator indicating the presence of a defect in said substrate.

Claim 4

Defect detecting apparatus for detecting a defect in a substrate including a defect at the periphery thereof, said substrate being sequentially scanned by an image pickup device along each of a plurality of vertically displaced horizontal lines for equal horizontal scanning periods, comprising: a binary coder coupled to the output of said image pickup device, said binary coder converting the output of said image pickup device to a binary coded signal having a polarity determined by the amount of light reflected from said substrate at each incremental portion of said scanning periods; a first shift register having an input coupled to the output of said binary coder and at least first and second outputs, the signal at said first output being delayed with respect to the signal at the input of said first shift register for an interval equal to said horizontal scanning period and the signal at said second output being delayed with respect to the signal at the input of said first shift register for a fixed interval less than said horizontal scanning period; a second shift register having an input coupled to the first output of said first shift register and at least a first output, the signal at the first output of said second shift register being delayed with respect to the signal at the input of said second shift register for a fixed interval equal to the fixed interval by which the second output of said first shift register is delayed with respect to the input of said first shift register; a first comparator having at least first and second inputs coupled to the first output of said second shift register and the second output of said first shift register respectively, said first comparator generating a signal at the output thereof when the signals at its first and second inputs are of predetermined opposite polarities; and a second comparator having at least first and second inputs coupled to the first output of said second shift register and to the second output of said first shift register respectively, said second comparator further having a third input coupled to the output of said first comparator, said second comparator generating a signal at the output thereof after generation of a signal at the output of said first comparator and when the signals at its first and second inputs are of polarities opposite the polarities of the first and second inputs respectively of said first comparator which caused generation of the output signal of said first comparator, generation of a signal at the output of said second comparator indicating the presence of a defect in said substrate.

Claim 5

A defect detecting apparatus as defined in claim 2 wherein said first shift register has at least one additional output delayed for a different specific interval than the second output of said first shift register and less than said horizontal scanning period, said second shift register has a corresponding additional output delayed for a specific interval equal to the delay of the corresponding additional output of said first shift register, and said first and second comparators have additional inputs coupled to the additional outputs of said first and second shift registers.

Claim 6

A defect detecting apparatus as defined in claim 2 wherein each of said first and second comparators comprises first and second AND gates, a NOR gate and a flip-flop, the outputs of the first AND gate and the NOR gate being coupled to the input of the second AND gate, the output of the second AND gate being coupled to the input of the flip-flop, the output of the flip-flop of the first comparator being coupled to the set input of the flip-flop in said second comparator and the output of said second flip-flop generating the output signal of said second comparator; and wherein the second output of said first shift register is coupled to the input of the NOR gate of said first comparator and the first AND gate of said second comparator, and the first output of said second shift register is coupled to the input of the first AND gate of said first comparator and the NOR gate of said second comparator.

Claim 7

A defect detecting apparatus as defined in claim 3 wherein each of said first and second comparators comprises first and second AND gates, a NOR gate and a flip-flop, the outputs of the first AND gate and the NOR gate being coupled to the input of the second AND gate, the output of the second AND gate being coupled to the input of the flip-flop, the output of the flip-flop of the first comparator being coupled to the set input of the flip-flop in said second comparator and the output of said second flip-flop generating the output signal of said second comparator; and additional outputs of said first shift register are coupled to the input of the NOR gate of said first comparator and the first AND gate of second comparator, and the first and additional outputs of said second shift register are coupled to the input of the first AND gate of said first comparator and the NOR gate of said second comparator.

Claim 8

A defect detecting apparatus as defined in claim 5 which further comprises switching means interposed between the outputs of said first and second shift registers and the inputs of said first AND and NOR gates for switching selected outputs of said shift registers to the inputs of said gates, said switching means determining the resolution of said defect detecting apparatus.