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US4486719A Expired / Lapsed US ⏱️ 0.0 years remaining

Distributed amplifier

Assignee: Raytheon Co
•
Filing: 1982-07-01
•
Granted: 1984-12-04
•
Expires: 2002-07-01
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Abstract

Abstract A distributed amplifier having a plurality of successively coupled field effect transistors with cascaded gate electrodes and cascaded drain electrodes. A first one of such transistors has the gate electrode thereof coupled to an input terminal adapted to receive an input radio frequency signal and the drain electrode thereof coupled to a dc drain electrode bias circuit. The last one of the successively coupled field effect transistors has the gate electrode thereof coupled to a dc gate electrode bias circuit and a drain electrode coupled to a radio frequency output terminal which produces an amplified radio frequency signal. The source electrodes of the plurality of transistors are coupled to ground. A drain bias voltage source is coupled between ground and the drain electrode bias circuit, such bias circuit providing a direct current path between such drain bias voltage source and the drain electrodes of the transistors. The drain electrode dc bias circuit has a complex impedance with the real component thereof being provided, in part, by a resistor in such bias circuit. The resistor is coupled in series with a grounded high frequency by-pass capacitor and, hence, is not in the direct current path between the drain bias voltage source and the drain electrodes, but rather is in the radio frequency signal path to ground. With such arrangement, only a relatively small amount of dc power is dissipated by the resistor in such drain biasing circuit.

Inventors

  • 👤 Yalcin Ayasli

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 12:13
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/60; H03F3/605; H03F3/607

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 108 words
In combination: (a) a plurality of successively coupled transistors, each one thereof having an input electrode, an output electrode, and a grounded electrode, a first one of such transistors having the input electrode thereof coupled to an input terminal and a last one of such transistors having the output electrode thereof coupled to an output terminal; (b) means for interconnecting said input electrodes; and (c) means, coupled to the output electrodes of the plurality of transistors, for coupling a grounded bias voltage source to the plurality of output electrodes through a direct current path and including a resistor coupled in shunt between ground and the direct current path.
Claim 2
Dependent Claim 108 words
In combination: (a) a plurality of successively coupled transistors, each one thereof having an input electrode, an output electrode, and a grounded electrode, a first one of such transistors having the input electrode thereof coupled to an input terminal and a last one of such transistors having the output electrode thereof coupled to an output terminal; (b) means for interconnecting said input electrodes; and (c) means, coupled to the output electrodes of the plurality of transistors, for coupling a grounded bias voltage source to the plurality of output electrodes through a direct current path and including a resistor coupled in shunt between ground and the direct current path.
Claim 3
Dependent Claim 22 words
The combination recited in claim 1 wherein the bias voltage coupling means includes a transmission line disposed in the direct current path.
Claim 4
Dependent Claim 31 words
The combination recited in claim 2 wherein the bias voltage coupling means includes a capacitor serially coupled to the resistor in the shunt path between the direct current path and ground.
Claim 5
Dependent Claim 130 words
A distributed amplifier, comprising: (a) means, including a plurality of successively coupled field effect transistors having cascade interconnected gate electrodes, cascade interconnected drain electrodes, and grounded source electrodes, a first one of such transistors having the gate electrode thereof coupled to an input terminal adapted to receive a radio frequency signal and the last one of the successively coupled transistors having the drain electrode thereof coupled to an output terminal for producing an amplified radio frequency signal; and, (b) drain bias circuit means connected to the drain electrodes of the transistors for coupling a grounded drain electrode bias voltage source to the drain electrodes through a series direct current path, and including a capacitor serially coupled to a resistor and coupled in shunt between the direct current path and ground.
Claim 6
Dependent Claim 130 words
A distributed amplifier, comprising: (a) means, including a plurality of successively coupled field effect transistors having cascade interconnected gate electrodes, cascade interconnected drain electrodes, and grounded source electrodes, a first one of such transistors having the gate electrode thereof coupled to an input terminal adapted to receive a radio frequency signal and the last one of the successively coupled transistors having the drain electrode thereof coupled to an output terminal for producing an amplified radio frequency signal; and, (b) drain bias circuit means connected to the drain electrodes of the transistors for coupling a grounded drain electrode bias voltage source to the drain electrodes through a series direct current path, and including a capacitor serially coupled to a resistor and coupled in shunt between the direct current path and ground.
Claim 7
Dependent Claim 37 words
The distributed amplifier recited in claim 4 including, additionally, a gate bias circuit means connected to the gate electrodes of the transistors for coupling a gate electrode bias voltage source to the gate electrodes of the transistors.
Claim 8
Dependent Claim 26 words
The distributed amplifier recited in claim 5 including a resistor disposed in a series path between the gate electrode bias voltage source and the gate electrodes.
Claim 9
Dependent Claim 23 words
The distributed amplifier recited in claim 6 wherein the gate bias circuit means includes a capacitor disposed between the series path and ground.
Claim 10
Dependent Claim 24 words
The distributed amplifier recited in claim 7 wherein the gate bias circuit means includes a radio frequency transmission line disposed in the series path.
Claim 11
Dependent Claim 22 words
The distributed amplifier recited in claim 8 including a plurality of transmission lines for successively coupling the plurality of field effect transistors.
Claim 12
Dependent Claim 22 words
The distributed amplifier recited in claim 9 wherein the drain bias circuit means includes a transmission line in the direct current path.

References Cited (Backward Citations)

AT280348B Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1987-12-04 1988-06-04 1988-12-04 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1991-12-04 1992-06-04 1992-12-04 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1995-12-04 1996-06-04 1996-12-04 $7700.00 Window Closed / Lapsed

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