Carrier wave regenerating circuit

Claim 1

A circuit for regenerating a carrier wave on the basis of a modulated wave, comprising a voltage-controlled oscillator having a control input and an output supplying the carrier wave, a first demodulator with two inputs, one receiving the modulated wave and the other being connected to the output of the oscillator, a second demodulator with two inputs, one receiving the modulated wave and the other being connected to the oscillator through a 90° phase shifter, each demodulator supplying a demodulated signal, respectively X for the first and Y for the second, and means for processing the signals X and Y for producing an error signal ε(φ), which is applied to the input of the oscillator and which is able to modify the phase of the latter in order to make it equal to the modulated wave, wherein the processing means makes it possible to produce an error signal comprising: a first decision and regeneration circuit with an input connected to the first demodulator and an output supplying a difference signal (X-X), in which X is a signal regenerated from signal X; a first zero threshold comparator with an input connected to the first modulator and an output supplying a signal determining the sign of X, i.e. sgn X; a second zero threshold comparator connected to the output of the decision and regeneration circuit and determining the sign of the difference X-X, i.e. sgn (X-X); a second decision and regeneration circuit with an input connected to the second democulator and an output supplying a difference signal (Y-Y), in which Y is a signal regenerated from signal Y; a third zero threshold comparator with an input connected to the second demodulator and an output supplying a signal determining the sign of Y, i.e. sgn Y; a fourth zero threshold comparator connected to the output of the second decision and regeneration circuit and determining the sign of the difference Y-Y, i.e. sgn (Y-Y); a first logic EXCLUSIVE-OR gate with two inputs, one connected to the output of the third comparator and receiving sgn (X-X) and the other to the output of the second comparator and receiving sgn (Y), said first gate supplying to an output a signal sgn (X-X) sgn (Y); a second EXCLUSIVE-OR gate with two inputs, one connected to the output of the fourth comparator and receiving sgn (Y-Y) and the other to the output of the second comparator and receiving sgn (X), said second gate supplying at an output a signal -sgn (Y-Y) sgn (X); an adder with two inputs, the first connected to the output of the first gate and the second to the output of the second gate, said adder supplying at a gate a signal sgn (X-X) sgn (Y)-sgn (Y-Y) sgn (X), which constitutes the error signal ε(φ), said output being connected to the control input of the voltage-sensitive oscillator.