Microprocessor bus interchange circuit

Claim 1

A bus interchange circuit for use with a primary processing unit, and a secondary processing unit, said secondary processing unit operated to generate an access request signal, said bus interchange circuit comprising: first detection means including a source of clock pulses and a shift register having a plurality of bit registers, each connected to said source of clock pulses, a first one of said bit registers being connected to said secondary processing unit, said shift register being operated in response to said clock pulses to sequentially clock the status of said access request signal through said shift register, whereby a first predetermined pattern of said shift register bits represents an access request detected signal of predetermined duration; gating means connected to said first detection means, operated in response to said access request detected signal to generate an access request interrupt signal of predetermined duration; said primary processor, connected to said gating means, operated in response to said access request interrupt signal to generate a grant signal; and second detection means connected to said primary processor, operated in response to said grant signal to generate an access request acknowledge signal; said shift register further operated in response to removal of said access request signal to provide a second predetermined pattern of shift register bits which represent an access removal detected signal of predetermined duration; said gating means further operated in response to said access removal detected signal to generate an access complete interrupt signal; and said second detection means further connected to said first duration means and further operated in response to said access removal detected signal to terminate said access request acknowledge signal.