US4482869A
Expired / Lapsed
US
⏱️ 0.0 years remaining
PLL Detection circuit having dual bandwidth loop filter
Assignee: Pioneer Corp
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Filing: 1982-04-13
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Granted: 1984-11-13
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Expires: 2002-04-13
Abstract
Abstract A PLL detection circuit for use in an AM-PM type AM stereo receiver in which unwanted AC signal components included in the output of a phase comparator are suppressed by switching the frequency response characteristic of a loop filter in the PLL detection circuit as locking is reached so that only the DC signal component, corresponding to the phase difference of the input signal and a reference signal, is outputted. A changeover circuit, including a switching circuit composed of a pair of parallel-connected transistors, is connected in parallel with an element of the loop filter, the component value of which affects or is at least partially determinative of the frequency response characteristic of the loop filter. The changeover circuit is activated by a control signal indicative of the locking state of the PLL detection circuit.
Inventors
- 👤 Hitoshi Hirata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 02:54
CPC Classifications
H; H03; H03D; H03D1/00; H03D1/22; H03D1/2245; H03D1/2254; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/10; H03L7/107; H03L7/1075; Y; Y10; Y10S; Y10S331/00; Y10S331/02
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
108 words
A PLL (phase locked loop) detection circuit, comprising: a loop filter comprising plural elements; a changeover circuit for switching a frequency response characteristic of said loop filter, and changeover circuit comprising a switching circuit including a pair of parallel-connected transistors, said switching circuit being connected across respective end terminals of a circuit which includes at least one of said plural loop filter elements; and actuating means for switching said pair of transistors in response to a predetermined control signal, said actuating means comprising a current mirror circuit having a two-stage configuration, outputs of said current mirror circuit stages being respectively connected to bases of said pair of transistors.
Claim 2
Dependent Claim
108 words
A PLL (phase locked loop) detection circuit, comprising: a loop filter comprising plural elements; a changeover circuit for switching a frequency response characteristic of said loop filter, and changeover circuit comprising a switching circuit including a pair of parallel-connected transistors, said switching circuit being connected across respective end terminals of a circuit which includes at least one of said plural loop filter elements; and actuating means for switching said pair of transistors in response to a predetermined control signal, said actuating means comprising a current mirror circuit having a two-stage configuration, outputs of said current mirror circuit stages being respectively connected to bases of said pair of transistors.
Claim 3
Dependent Claim
22 words
The PLL detection circuit as claimed in claim 1, wherein said at least one of said loop filter elements comprises a resistor.
Claim 4
Dependent Claim
33 words
The PLL detection circuit as claimed in claim 1, wherein said predetermined control signal comprises a lock detection signal having an actuated state corresponding to a locked state of said PLL detection circuit.
Claim 5
Dependent Claim
289 words
A PLL (phase locked loop) detection circuit comprising: a phase comparator receiving an input signal on a comparison input thereof; a buffer amplifier having an input coupled to an input coupled to an output of said buffer amplifier, said loop filter comprising at least one element a component value of which affects a frequency response characteristic of said loop filter; a DC amplifier having an input coupled to an output of said loop filter; a voltage-controlled oscillator having an input coupled to an output of said DC amplifier and an output coupled to a reference input of said phase comparator; a changeover circuit for switching said frequency response characteristic of said loop filter, said changeover circuit comprising a first transistor receiving on a control input thereof a predetermined control signal having a state indicative of a locked state of said PLL detection circuit, a current mirror circuit comprising a diode-connected second transistor having a collector and base coupled to a collector of said first transistor and third and fourth transistors having bases coupled to said base of said second transistor, emitters of said second, third and fourth transistors being coupled through respective resistors to a voltage source, and fifth and sixth transistors having bases connected to collectors of said third and fourth transistors, respectively, an emitter of said fifth transistor being coupled to a first terminal of said element of said loop filter, a collector of said fifth transistor being coupled through a resistor to a second terminal of said element of said loop filter, a collector of said sixth transistor being coupled through a resistor to said first terminal of said element and an emitter of said sixth transistor being coupled to said second terminal of said element.
Claim 6
Dependent Claim
289 words
A PLL (phase locked loop) detection circuit comprising: a phase comparator receiving an input signal on a comparison input thereof; a buffer amplifier having an input coupled to an input coupled to an output of said buffer amplifier, said loop filter comprising at least one element a component value of which affects a frequency response characteristic of said loop filter; a DC amplifier having an input coupled to an output of said loop filter; a voltage-controlled oscillator having an input coupled to an output of said DC amplifier and an output coupled to a reference input of said phase comparator; a changeover circuit for switching said frequency response characteristic of said loop filter, said changeover circuit comprising a first transistor receiving on a control input thereof a predetermined control signal having a state indicative of a locked state of said PLL detection circuit, a current mirror circuit comprising a diode-connected second transistor having a collector and base coupled to a collector of said first transistor and third and fourth transistors having bases coupled to said base of said second transistor, emitters of said second, third and fourth transistors being coupled through respective resistors to a voltage source, and fifth and sixth transistors having bases connected to collectors of said third and fourth transistors, respectively, an emitter of said fifth transistor being coupled to a first terminal of said element of said loop filter, a collector of said fifth transistor being coupled through a resistor to a second terminal of said element of said loop filter, a collector of said sixth transistor being coupled through a resistor to said first terminal of said element and an emitter of said sixth transistor being coupled to said second terminal of said element.
Claim 7
Dependent Claim
28 words
The PLL detection circuit as claimed in claim 4, wherein said loop filter comprises an RC loop filter and said element of said loop filter is a resistor.
References Cited (Backward Citations)
US4077015A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-11-13 | 1988-05-14 | 1988-11-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-11-13 | 1992-05-14 | 1992-11-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-11-13 | 1996-05-14 | 1996-11-13 | $7700.00 | Window Closed / Lapsed |