Dynamic Semiconductor memory device

Claim 2

A dynamic semiconductor memory device, operatively connected to receive a control signal, having word lines, a pair of bit lines intersecting the word lines and a sense amplifier operatively connected to the bit line pair, comprising: a selected real cell operatively connected to a first one of the word lines and a first bit line of the pair of bit lines; and an active restore circuit, operatively connected to the pair of bit lines, including bit line pull-up transistors, each of said bit line pull-up transistors operatively connected between the bit line pair and a high potential source level, the control signal being supplied to each of said bit line pull-up transistors after actuation of the sense amplifier, each of said bit line pull-up transistors being turned on so that the bit line pair is pulled up to the high potential source level, the level of said control signal being maintained at a voltage potential level lower than the ground level before or at the time of actuation of the first one of the word lines to the time of actuation of the sense amplifier.

Claim 3

A dynamic semiconductor memory device according to claim 1, wherein the circuit by which the level of the control signal is maintained at a voltage potential level lower than the ground level comprises: first and second transistors operatively connected in series and forming a first connection node therebetween, and operatively connected between the high potential source level and the ground level, each of said first and second transistors having a gate; third and fourth transistors, operatively connected in series and forming a second connection node therebetween, and operatively connected between the high potential source level and the ground level, each of said third and fourth transistors having a gate; and a capacitor connected between the first connection node and the second connection node, said second and third transistors being turned on so that the first connection node is maintained at the ground level and the second connection node is maintained at the high potential source level at the time of actuation of the first one of the word lines, said second and third transistors then being turned off, and a high level clock pulse signal being supplied to the gate of said fourth transistor so that a voltage level lower than the ground level is present at the first connection node, and when the sense amplifier is actuated, a pulse having a value higher than the high potential source level is supplied to the gate of said first transistor.

Claim 4

A dynamic semiconductor device operatively connectable to receive a high potential source level, comprising: a sense amplifier; a pair of bit lines operatively connected to said sense amplifier; word lines intersecting said pair of bit lines; a memory cell operatively connected to one of said word lines; and an active restore circuit, operatively connected to said pair of bit lines, comprising: means for generating a control signal, the control signal having a voltage potential lower than ground level during a predetermined time; and bit line pull-up transistors, operatively connected to said pair of bit lines and said control signal generating means and operatively connected to receive the high potential source level, said bit line pull-up transistors being turned on upon receipt of the control signal to pull-up said bit line pairs to the high potential source level.

Claim 5

A dynamic semiconductor device operatively connectable to receive a high potential source level, comprising: a sense amplifier; a pair of bit lines operatively connected to said sense amplifier; word lines intersecting said pair of bit lines; a memory cell operatively connected to one of said word lines; and an active restore circuit, operatively connected to said pair of bit lines, comprising: means for generating a control signal, the control signal having a voltage potential lower than ground level during a predetermined time; and bit line pull-up transistors, operatively connected to said pair of bit lines and said control signal generating means and operatively connected to receive the high potential source level, said bit line pull-up transistors being turned on upon receipt of the control signal to pull-up said bit line pairs to the high potential source level.

Claim 6

A semiconductor memory device according to claim 3, wherein said means for generating the control signal comprises: a first transistor operatively connected to receive the high potential source level; a second transistor operatively connected to said first transistor at a first connection node and operatively connected to ground; a third transistor operatively connected to receive the high potential source level; a fourth transistor operatively connected to said third transistor at a second connection node and operatively connected to ground; and a capacitor operatively connected between the first and second connection nodes, wherein when said second and third transistors are turned on, the first connection node is at ground level and the second connection node is at the high potential source level, and wherein when said second and third transistors are turned off the first connection node is at a level lower than ground level.