Self regenerative fast gate turn-off FET

Claim 2

A fast turn-off FET circuit having drain, source and gate terminals, comprising: an enhancement mode FET having a drain connected to said drain terminal, a source connected to said source terminal, and a gate operatively coupled to said gate terminal; regenerative switch means connected to said FET gate and source and driven into latched conduction by residual stored charge in the gate to source capacitance of said FET upon turn-off of the latter due to removal of gate drive, said conduction of said regenerative switch means remaining latched ON until the charge on said FET gate is depleted to a given switching threshold, such that conduction of said regenerative switch means provides faster discharge therethrough of said FET gate, whereby to facilitate faster FET turn-off.

Claim 3

The invention according to claim 1 comprising gate biasing voltage source means for supplying gate drive to said gate terminal, and wherein said regenerative switch means comprises regeneratively coupled bipolar transistor means connected between said FET gate and said FET source, and biased OFF in response to gate drive to said FET to prevent draining of said gate drive away from said FET gate.

Claim 4

The invention according to claim 2 wherein said regeneratively coupled bipolar transistor means comprise first bipolar transistor means having one of its emitter and collector connected to said FET gate and having a base connected to said gate terminal, and second bipolar transistor means having one of its emitter and collector coupled to said base of said first bipolar transistor means and having the other of its emitter and collector connected to said FET source and having a base connected to the other of said emitter and collector of said first bipolar transistor means, such that the base drive for said second bipolar transistor means is supplied by conduction of said first bipolar transistor means and such that the base drive of said first bipolar transistor means is supplied by conduction of said second bipolar transistor means.

Claim 5

The invention according to claim 3 comprising a diode connected between said gate terminal and said FET gate, said base of said first bipolar transistor means and said one of said emitter and collector of said second bipolar transistor means being connected to a node connecting said gate terminal and said diode, and said one of said emitter and collector of said first bipolar transistor means being connected to a node connecting said diode and said FET gate, said diode being forward biased in response to gate drive to pass gate drive therethrough to drive said FET gate, said diode being reverse biased in response to gate to source capacitive voltage of said FET upon removal of gate drive whereby to block current flow through said diode between said FET gate and said base of said first bipolar transistor means and said one of said emitter and collector of said second bipolar transistor means and insure biasing of said regeneratively coupled bipolar transistor means into conduction.

Claim 6

The invention according to claim 4 comprising resistor means connected between said base of said first bipolar transistor means and said FET source, said resistor means being of a sufficient value to prevent significant diversion of gate drive from said gate terminal to said FET source and to provide a return path for biasing said first bipolar transistor means into conduction.

Claim 7

The invention according to claim 5 comprising second resistor means connected between said base of second bipolar transistor means and said FET source to prevent high temperature leakage in said second bipolar transistor means from causing excessive gate drive requirements into said gate terminal.

Claim 8

The invention according to claim 5 wherein said first bipolar transistor means comprises a Darlington connected transistor pair, and further comprising a resistor having one end connected to a node connecting said gate terminal and the base of said Darlington transistor pair, and having its other end connected to said one of said emitter and collector of said second bipolar transistor means, said last mentioned resistor facilitating turn-on of said FET if required before said regeneratively looped bipolar transistor means has turned off by diverting reapplied base drive to said base of said Darlington transistor pair to reverse bias the emitter-base junction of the latter to turn it off and break the regenerative loop, and preventing a short circuit through said second bipolar transistor means.

Claim 9

A fast turn-off FET circuit having drain, source and gate terminals comprising: an n channel enhancement mode FET having a drain connected to said drain terminal, a source connected to said source terminal, and a gate operatively coupled to said gate terminal; a diode having a cathode connected to said FET gate and an anode connected to said gate terminal; a PNP bipolar transistor having its emitter connected to a node connecting said diode and said FET gate; an NPN bipolar transistor having a collector connected to the base of said first bipolar transistor and connected in common therewith to a node connecting said gate terminal and said diode, the base of said NPN transistor connected to the collector of said PNP transistor, the emitter of said NPN transistor connected to said FET source.

Claim 10

A fast turn-off FET circuit having drain, source and gate terminals comprising: an n channel enhancement mode FET having a drain connected to said drain terminal, a source connected to said source terminal, and a gate operatively coupled to said gate terminal; a diode having a cathode connected to said FET gate and an anode connected to said gate terminal; a PNP bipolar transistor having its emitter connected to a node connecting said diode and said FET gate; an NPN bipolar transistor having a collector connected to the base of said first bipolar transistor and connected in common therewith to a node connecting said gate terminal and said diode, the base of said NPN transistor connected to the collector of said PNP transistor, the emitter of said NPN transistor connected to said FET source.

Claim 11

The invention according to claim 8 comprising a resistor connected between said base of said PNP transistor and said FET source, said bipolar transistors forming a regenerative loop driven into latched conduction by residual stored charge in the gate to source capacitance of said FET upon turn-off of the latter due to removal of gate drive, said diode being reverse biased and the emitter-base junction of said PNP transistor being forward biased by said residual capacitively stored gate charge upon removal of gate drive, such that said PNP transistor is biased into conduction and supplies base drive to said NPN transistor to render the latter conductive which in turn latches base drive from said PNP transistor to complete said regenerative loop which remains conducting until said FET gate charge is depleted to a given switching threshold, such that latched conduction of said bipolar transistors provides faster discharge therethrough of said FET gate, whereby to facilitate faster FET turn-off, said connection of said base of said PNP transistor to said gate terminal causing said PNP transistor to be biased OFF in response to gate drive to said FET to prevent draining of said gate drive away from said FET gate, said reverse biased condition of said diode upon removal of gate drive causing said diode to block current flow therethrough from said FET gate to said base of said PNP transistor and insure biasing of said PNP transistor into conduction.