US4480268A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Gamma correction circuit
Assignee: Hitachi Ltd
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Filing: 1982-06-02
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Granted: 1984-10-30
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Expires: 2002-06-02
Abstract
Abstract A gamma correction circuit is provided with a first circuit including a first linear element and a first non-linear element connected in series in the above order and a second circuit including a second non-linear element and a second linear element connected in series in the above order. A first connection point is located between the first linear element and the second non-linear element and a second connection point is located between the first non-linear element and the second linear element. A current source for converting a video signal voltage into a current output is connected to the second connection point. Two common collector (or common drain) transistors have their collectors (or their drains) connected to a power supply line. The input terminals of these transistors are connected to the connection point between the first linear element and the first non-linear element and to the connection point between the second non-linear element and the second linear element respectively, and the output terminals are connected to each other through a resistor. In order to decrease the junction capacitance of the transistors as the video signal voltage level increases, a voltage regulator circuit is connected between the power supply line and the first connection point.
Inventors
- 👤 Michitaka Osawa
- 👤 Hitoshi Maekawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 22:45
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/14; H04N5/20; H04N5/202
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
241 words
A gamma correction circuit comprising: (a) a signal source; (b) a DC power source; (c) first biasing means connected at one of its terminals to said signal source and at the other terminal to said DC power source and generating at a terminal intermediate between said terminals a voltage varying in linear relation to a signal applied from said signal source; (d) second biasing means connected at one of its terminals to said signal source and at the other terminal to said DC power source and generating at a terminal intermediate between said terminals a voltage varying in non-linear relation to the signal applied from said signal source; (e) a first transistor including a common terminal, an output terminal and an input terminal connected to the intermediate terminal of said first biasing means; (f) a second transistor including a common terminal, an output terminal and an input terminal connected to the intermediate terminal of said second biasing means; (g) signal combining means connected to the output terminals of said first and second transistors for combining the signals appearing at said output terminals; and (h) voltage supplying means for supplying a first DC voltage to the common terminals of said first and second transistors and for supplyig to said other terminals of said first and second biasing means a second DC voltage deviating from said first DC voltage in a direction tending to decrease the junction capacitance of each of said transistors.
Claim 2
Dependent Claim
241 words
A gamma correction circuit comprising: (a) a signal source; (b) a DC power source; (c) first biasing means connected at one of its terminals to said signal source and at the other terminal to said DC power source and generating at a terminal intermediate between said terminals a voltage varying in linear relation to a signal applied from said signal source; (d) second biasing means connected at one of its terminals to said signal source and at the other terminal to said DC power source and generating at a terminal intermediate between said terminals a voltage varying in non-linear relation to the signal applied from said signal source; (e) a first transistor including a common terminal, an output terminal and an input terminal connected to the intermediate terminal of said first biasing means; (f) a second transistor including a common terminal, an output terminal and an input terminal connected to the intermediate terminal of said second biasing means; (g) signal combining means connected to the output terminals of said first and second transistors for combining the signals appearing at said output terminals; and (h) voltage supplying means for supplying a first DC voltage to the common terminals of said first and second transistors and for supplyig to said other terminals of said first and second biasing means a second DC voltage deviating from said first DC voltage in a direction tending to decrease the junction capacitance of each of said transistors.
Claim 3
Dependent Claim
25 words
A gamma correction circuit as claimed in claim 1, wherein said DC power source includes a voltage regulator circuit connected to said voltage supplying means.
Claim 4
Dependent Claim
18 words
A gamma correction circuit as claimed in claim 2, wherein said voltage regulator circuit includes a Zener diode.
Claim 5
Dependent Claim
237 words
A gamma correction circuit comprising: (a) a signal source; (b) a first circuit including an output terminal generating a voltage varying the linear relation to a signal applied from said signal source; (c) a second circuit including an output terminal generating a voltage varying in non-linear relation to the signal applied from said signal source; (d) a first transistor including a common terminal, an output terminal and an input terminal connected to the output terminal of said first circuit; (e) a second transistor including a common terminal, an output terminal and an input terminal connected to the output terminal of said second circuit; (f) signal combining means for combining the signals appearing at the output terminals of said first and second transistors; (g) first biasing means for reverse biasing, through a portion of said first circuit, the diode junction formed between the input terminal and the common terminal of said first transistor; (h) second biasing means for reverse biasing, through a portion of said second circuit, the diode junction formed between the input terminal and the common terminal of said second transistor; and (i) voltage supply means for supplying a first DC voltage to the common terminals of said first and second transistors and for supplying to said first and second biasing means a second DC voltage deviating from said first DC voltage in a direction tending to decrease the junction capacitance of each of said transistors.
Claim 6
Dependent Claim
237 words
A gamma correction circuit comprising: (a) a signal source; (b) a first circuit including an output terminal generating a voltage varying the linear relation to a signal applied from said signal source; (c) a second circuit including an output terminal generating a voltage varying in non-linear relation to the signal applied from said signal source; (d) a first transistor including a common terminal, an output terminal and an input terminal connected to the output terminal of said first circuit; (e) a second transistor including a common terminal, an output terminal and an input terminal connected to the output terminal of said second circuit; (f) signal combining means for combining the signals appearing at the output terminals of said first and second transistors; (g) first biasing means for reverse biasing, through a portion of said first circuit, the diode junction formed between the input terminal and the common terminal of said first transistor; (h) second biasing means for reverse biasing, through a portion of said second circuit, the diode junction formed between the input terminal and the common terminal of said second transistor; and (i) voltage supply means for supplying a first DC voltage to the common terminals of said first and second transistors and for supplying to said first and second biasing means a second DC voltage deviating from said first DC voltage in a direction tending to decrease the junction capacitance of each of said transistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-10-30 | 1988-04-30 | 1988-10-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-10-30 | 1992-04-30 | 1992-10-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-10-30 | 1996-04-30 | 1996-10-30 | $7700.00 | Window Closed / Lapsed |