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US4479188A Expired / Lapsed US ⏱️ 0.0 years remaining

Digital detector for a multi-frequency code in an analog signal

Assignee: STAAT DER NEDERLANDEN (STAATSBEDRIJF DER POSTERIJEN TELEGRAFIE EN TLEPHONE) 12 NETHERLANDS
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Filing: 1982-08-25
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Granted: 1984-10-23
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Expires: 2002-08-25
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Abstract

Abstract This disclosure concerns a system for digitally detecting one or more of a plurality of fixed frequencies in an analog signal according to a correlation method, the fixed frequencies occurring in a first group and in a second group wherein a third harmonic of one or more frequencies of the first group is equal or almost equal to a frequency of the second group. Each of the frequencies of the first group are represented by a sequence of six equidistant pulses per period, which pulses have the values +1, +1, 0, -1, -1 and 0, respectively; and the frequencies of the second group are represented by a sequence of two equidistant pulses per period, which pulses have the values +1 and -1, respectively. All these reference pulses can be stored in a reference memory (5) which is read out at a frequency whose value is equal to the product of the number of memory places in the reference memory, and the frequency which is the highest common factor of the frequencies to be detected.

Inventors

  • 👤 Johannes de Keijzer

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 05:25
CPC Classifications
H; H04; H04Q; H04Q1/00; H04Q1/18; H04Q1/30; H04Q1/44; H04Q1/444; H04Q1/45; H04Q1/457

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 269 words
An apparatus for digitally detecting one or more of a plurality of fixed frequencies which are present in an incoming signal according to the correlation method, the fixed frequencies occurring in a first group of lower frequencies and in a second group of higher frequencies, said apparatus comprising: (a) means (2) for sampling the incoming analog signal of said fixed frequencies, (b) a reference memory means (5) having separate registers in which are stored sine reference code number pulses and a cosine reference code number pulses for a whole number of periods of each of the frequencies to be detected, the lower group of frequencies having six code number pulses per period which pulses have the values of +1, +1, 0, -1, -1, 0, and in the higher group of frequencies having two pulses per period, which pulses have the values of +1 and -1, (c) means (4) for the multiplication of the samples of said incoming signals with said reference code number pulses, (d) means (6) for adding the resulting multiplication products, (e) means (7) for comparing and selecting the highest valued multiplied product as corresponding to the frequency to be detected, and (f) a clock pulse and control circuit (3) means for controlling all of the above mentioned means including sampling the analog input signal at frequency the value of which is equal to a product of the number of code number pulses in said reference memory means and the frequency which is the highest common factor of the frequencies to be detected, and reading out said reference memory means said sine-cosine values at said sampling frequency.
Claim 2
Independent Claim 269 words
An apparatus for digitally detecting one or more of a plurality of fixed frequencies which are present in an incoming signal according to the correlation method, the fixed frequencies occurring in a first group of lower frequencies and in a second group of higher frequencies, said apparatus comprising: (a) means (2) for sampling the incoming analog signal of said fixed frequencies, (b) a reference memory means (5) having separate registers in which are stored sine reference code number pulses and a cosine reference code number pulses for a whole number of periods of each of the frequencies to be detected, the lower group of frequencies having six code number pulses per period which pulses have the values of +1, +1, 0, -1, -1, 0, and in the higher group of frequencies having two pulses per period, which pulses have the values of +1 and -1, (c) means (4) for the multiplication of the samples of said incoming signals with said reference code number pulses, (d) means (6) for adding the resulting multiplication products, (e) means (7) for comparing and selecting the highest valued multiplied product as corresponding to the frequency to be detected, and (f) a clock pulse and control circuit (3) means for controlling all of the above mentioned means including sampling the analog input signal at frequency the value of which is equal to a product of the number of code number pulses in said reference memory means and the frequency which is the highest common factor of the frequencies to be detected, and reading out said reference memory means said sine-cosine values at said sampling frequency.
Claim 3
Dependent Claim 33 words
An apparatus according to claim 1 including means for reading out said number code pulses from said reference memory means at equally spaced intervals per whole period of the frequencies to be detected.

References Cited (Backward Citations)

US3636333A Cited
US3881101A Cited
US4100378A Cited
US4038540A Cited
US4185172A Cited
US4088960A Cited
US4370726A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1987-10-23 1988-04-23 1988-10-23 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1991-10-23 1992-04-23 1992-10-23 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1995-10-23 1996-04-23 1996-10-23 $7700.00 Window Closed / Lapsed

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