US4479126A
Expired / Lapsed
US
⏱️ 0.0 years remaining
MIS Decoder circuit
Assignee: Fujitsu Ltd
•
Filing: 1982-06-28
•
Granted: 1984-10-23
•
Expires: 2002-06-28
Abstract
Abstract A decoder circuit, used, for example, in a semiconductor memory device, decodes an n bit address signal and selects one of 2 n output lines such as word lines or bit lines. In the decoder circuit, MIS transistors connected to decoded signal output lines are commonly used by adjacent decoded signal output lines, so that the area occupied by the decoder circuit is decreased and the degree of integration is increased.
Inventors
- 👤 Mitsuo Higuchi
- 👤 Hideki Arakawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:27
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/10
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
218 words
A decoder circuit, having a load element operatively connected to a power source, for decoding an n bit (n is a positive integer) address signal to select one of 2 n output lines, said decoder circuit comprising: 2 n +2 first MIS transistors arranged in a row for decoding a first bit of said address signal, each of said first MIS transistors having a source operatively connected to ground and having a drain operatively connected to the load element and one of said output lines; first means, operatively connected to said 2 n +2 first MIS transistors, for decoding a second through m-th bit (m is a positive integer smaller than n) of said address signal, said first means comprising m-1 second MIS transistors operatively connected in parallel with each other between said drains of first alternate pairs of adjacent said first MIS transistors along said row; and second means, operatively connected to said 2 n +2 first MIS transistors, for decoding an (m+1)-th through an n-th bit of said address signal, said second means comprising n-m third MIS transistors operatively connected in parallel with each other between said drains of second alternate pairs of adjacent said first MIS transistors along said row and each having a gate, said first and second means arranged alternately along said row.
Claim 2
Dependent Claim
218 words
A decoder circuit, having a load element operatively connected to a power source, for decoding an n bit (n is a positive integer) address signal to select one of 2 n output lines, said decoder circuit comprising: 2 n +2 first MIS transistors arranged in a row for decoding a first bit of said address signal, each of said first MIS transistors having a source operatively connected to ground and having a drain operatively connected to the load element and one of said output lines; first means, operatively connected to said 2 n +2 first MIS transistors, for decoding a second through m-th bit (m is a positive integer smaller than n) of said address signal, said first means comprising m-1 second MIS transistors operatively connected in parallel with each other between said drains of first alternate pairs of adjacent said first MIS transistors along said row; and second means, operatively connected to said 2 n +2 first MIS transistors, for decoding an (m+1)-th through an n-th bit of said address signal, said second means comprising n-m third MIS transistors operatively connected in parallel with each other between said drains of second alternate pairs of adjacent said first MIS transistors along said row and each having a gate, said first and second means arranged alternately along said row.
Claim 3
Dependent Claim
23 words
A decoder circuit according to claim 1, wherein said load element is a depletion-type MIS transistor having a gate and source commonly connected.
Claim 4
Dependent Claim
45 words
A decoder circuit according to claim 1 or 2, wherein each of said gates of said first MIS transistors is supplied with an inverted signal of the first bit of said address signal or a noninverted signal of the first bit of said address signal.
Claim 5
Dependent Claim
20 words
A decoder circuit according to claim 3, wherein said first bit is the least significant bit of said address signal.
Claim 6
Dependent Claim
41 words
A decoder circuit according to claim 1 or 2, wherein each of said gates of said second MIS transistors is supplied with an inverted signal or a noninverted signal of one of the second through m-th bits of said address signal.
Claim 7
Dependent Claim
41 words
A decoder circuit according to claim 1 or 2, wherein each of said gates of said third MIS transistors is supplied with an inverted signal or a noninverted signal of one of the (m+1)-th through n-th bits of said address signal.
Claim 8
Dependent Claim
29 words
A decoder circuit according to claim 1, wherein said decoder circuit is a word address decoder of a semiconductor memory device and the output lines are word lines thereof.
Claim 9
Dependent Claim
29 words
A decoder circuit according to claim 1, wherein said decoder circuit is a bit address decoder of a semiconductor memory device and the output lines are bit lines thereof.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-10-23 | 1988-04-23 | 1988-10-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-10-23 | 1992-04-23 | 1992-10-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-10-23 | 1996-04-23 | 1996-10-23 | $7700.00 | Window Closed / Lapsed |