← Back to Patent Explorer
US4476399A Expired / Lapsed US ⏱️ 0.0 years remaining

Stabilized power source parallel operation system

Assignee: Fuji Electric Co Ltd
•
Filing: 1983-06-07
•
Granted: 1984-10-09
•
Expires: 2003-06-07
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A stabilized power source parallel operation system in which the composite output current is maintained at a predetermined level even if a plurality of the parallel power sources are deenergized. Each power source has a voltage comparator, a current converter and a current comparator. The outputs of each of the voltage comparators are interconnected by an inter-power source voltage bus so that each of the current comparators compare the same current.

Inventors

  • 👤 Masahiro Yoshida
  • 👤 Masahiko Oka

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 19:00
CPC Classifications
G; G05; G05F; G05F1/00; G05F1/10; G05F1/46; G05F1/56; G05F1/59

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 169 words
A stabilized power source parallel operation system comprising a plurality of stabilized power sources connected in parallel to one another, each of said power sources producing an output voltage and an output current, each of said sources comprising: an error voltage detecting means for comparing a reference voltage and said output voltage and outputting an error voltage indicative of a difference therebetween; an output current detecting means for detecting an output current of said power source and for outputting an detection voltage corresponding to the output current thus detected; a current adjusting means for adjusting an output current of said power source so that the detection voltage of said output current detecting means is equal to the current set value; and a common bus means for interconnecting the outputs of said error voltage detecting means of each of said power sources, said error voltages thereof being combined in said bus to produce an averaged current set value for setting each of said current set values of said power sources.
Claim 2
Dependent Claim 169 words
A stabilized power source parallel operation system comprising a plurality of stabilized power sources connected in parallel to one another, each of said power sources producing an output voltage and an output current, each of said sources comprising: an error voltage detecting means for comparing a reference voltage and said output voltage and outputting an error voltage indicative of a difference therebetween; an output current detecting means for detecting an output current of said power source and for outputting an detection voltage corresponding to the output current thus detected; a current adjusting means for adjusting an output current of said power source so that the detection voltage of said output current detecting means is equal to the current set value; and a common bus means for interconnecting the outputs of said error voltage detecting means of each of said power sources, said error voltages thereof being combined in said bus to produce an averaged current set value for setting each of said current set values of said power sources.
Claim 3
Dependent Claim 50 words
The stabilized power source parallel operating system as recited in claim 1 wherein said output current detecting means comprises a mixing resistor which is connected between said error voltage detecting means and said common bus means, and a voltage follower connected between said bus means and said current adjusting means.
Claim 4
Dependent Claim 125 words
The stabilized power source parallel operating system as recited in claim 2, wherein said average current set value V isN for an Nth of said power sources is defined by the equation: ##EQU6## where R11, R21, . . . RN1 are the resistances of the mixing resistors of each of the first, second, . . . Nth power sources respectively, Z i =(Z i1 / /Z i2 / / . . . Z iN ) is the combined input impedance of the voltage followers of all of the first, second, . . . Nth power sources, and V i1 , V i2 , . . . V iN are the error voltages of each of the first, second, . . . Nth power sources, respectively.

References Cited (Backward Citations)

US3956638A Cited
US4318007A Cited
US4356403A Cited
US4429233A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1987-10-09 1988-04-09 1988-10-09 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1991-10-09 1992-04-09 1992-10-09 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1995-10-09 1996-04-09 1996-10-09 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag