US4475237A
Expired / Lapsed
US
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Programmable range recognizer for a logic analyzer
Assignee: Micron Technology Inc
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Filing: 1981-11-27
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Granted: 1984-10-02
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Expires: 2001-11-27
Abstract
Abstract A programmable range recognizer produces a recognition signal whenever a digital word occurs within a specified closed range of digital words. Such a programmable range recognizer is useful for triggering or data qualification in a logic state analyzer. The range recognizer comprises a random-access memory divided into a plurality of sections, each for decoding a corresponding byte of the digital word, and a combination logic circuit for combining decoded bits to produce a recognition output.
Inventors
- 👤 Dennis E. Glasby
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 00:20
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/25; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3177; G06F7/00; G06F7/02; G06F7/026
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
126 words
A method of recognizing digital words occurring within a closed range of such words, comprising the steps of: (a) splitting the digital words into a plurality of word segments each defining a range of numbers having an upper bound and a lower bound; (b) decoding each of said word segments in a separate memory section programmed with predetermined upper bound and lower bound values and producing output bits when the numerical value of each of said word segments is equal to one of said predetermined upper bound and lower bound values, and when the numerical value of each of said word segments is between said predetermined upper bound and lower bound values; and (c) combining ones of said output bits to thereby produce a recognition output.
Claim 2
Independent Claim
126 words
A method of recognizing digital words occurring within a closed range of such words, comprising the steps of: (a) splitting the digital words into a plurality of word segments each defining a range of numbers having an upper bound and a lower bound; (b) decoding each of said word segments in a separate memory section programmed with predetermined upper bound and lower bound values and producing output bits when the numerical value of each of said word segments is equal to one of said predetermined upper bound and lower bound values, and when the numerical value of each of said word segments is between said predetermined upper bound and lower bound values; and (c) combining ones of said output bits to thereby produce a recognition output.
Claim 3
Dependent Claim
38 words
A method in accordance with claim 1 wherein said word segments are bytes ranging from most significant to least significant, and wherein said decoding is done by a random-access memory having a memory section corresponding to each byte.
Claim 4
Independent Claim
127 words
A system for recognizing digital words occuring within a closed range of such words, comprising: means for splitting the digital words into a plurality of word segments each defining a range of numbers having an upper bound and a lower bound; means for decoding each of said word segments in a separate memory section programmed with predetermined upper bound and lower bound values and producing decoded output bits when the numerical value of each of said word segments is equal to one of said predetermined upper bound and lower bound values, and when the numerical value of each of said word segments is between said predetermined upper bound and lower bound values; and means for combining ones of said output bits to thereby product a recognition output.
Claim 5
Independent Claim
127 words
A system for recognizing digital words occuring within a closed range of such words, comprising: means for splitting the digital words into a plurality of word segments each defining a range of numbers having an upper bound and a lower bound; means for decoding each of said word segments in a separate memory section programmed with predetermined upper bound and lower bound values and producing decoded output bits when the numerical value of each of said word segments is equal to one of said predetermined upper bound and lower bound values, and when the numerical value of each of said word segments is between said predetermined upper bound and lower bound values; and means for combining ones of said output bits to thereby product a recognition output.
Claim 6
Dependent Claim
37 words
A system in accordance with claim 3 wherein said word segments are bytes ranging from most significant to least significant, and wherein said decoding means comprises random-access memory means having a memory section corresponding to each byte.
Claim 7
Dependent Claim
45 words
A system in accordance with claim 4 wherein each of said memory sections is divided into subsections each containing one of an upper bound value, a lower bound value, and a range of values, wherein output bits may be provided by one or more subsections.
Claim 8
Dependent Claim
14 words
A system in accordance with claim 4 wherein said random-access memory means is programmable.
Claim 9
Dependent Claim
101 words
A programmable range recognizer, comprising: means for splitting digital words into bytes ranging from a most significant byte to a least significant byte; a random-access memory having a plurality of sections, each section corresponding to a respective one of said bytes and being divided into subsections each containing one of a stored upper bound value, lower bound value, and a range of values therebetween, wherein decoded output bits are provided from said subsections when the byte value is true; and a combination logic circuit comprising a plurality of logic elements for combining said output bits to produce a range recognition signal.
Claim 10
Dependent Claim
101 words
A programmable range recognizer, comprising: means for splitting digital words into bytes ranging from a most significant byte to a least significant byte; a random-access memory having a plurality of sections, each section corresponding to a respective one of said bytes and being divided into subsections each containing one of a stored upper bound value, lower bound value, and a range of values therebetween, wherein decoded output bits are provided from said subsections when the byte value is true; and a combination logic circuit comprising a plurality of logic elements for combining said output bits to produce a range recognition signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-10-02 | 1988-04-02 | 1988-10-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-10-02 | 1992-04-02 | 1992-10-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-10-02 | 1996-04-02 | 1996-10-02 | $7700.00 | Window Closed / Lapsed |