US4473785A
Expired / Lapsed
US
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Numerical control unit
Assignee: Fanuc Corp
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Filing: 1981-07-16
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Granted: 1984-09-25
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Expires: 2001-07-16
Abstract
Abstract A numerical control unit which includes a main bus connected to (a main processor) operates, according to an execution program stored in a main memory, on data from the memory or a tape reader, and applies the results of the operation to axis-control circuits in order to perform predetermined numerical control. The main memory and buffer circuits (4a to 4c in FIG. 1) are connected to the main bus. This minimizes the electrical load on the main processor. Peripheral buses are provided for each of the buffer circuits, and peripheral hardware and the axis-control circuits of individual package units are each connected to the peripheral buses.
Inventors
- 👤 Mitsuo Kurakake
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 06:00
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/18; G05B19/414; G05B19/4141; G05B2219/00; G05B2219/30; G05B2219/33; G05B2219/33337
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
118 words
An improved numerical control unit of the type which employs a plurality of control circuits and which performs data processing using a processor having a main bus connected thereto, wherein the improvement comprises: a plurality of first circuit blocks, each with a peripheral bus having connected thereto only axis-control circuits; a second circuit block with a peripheral bus having connected thereto circuits other than the axis-control circuits; and a plurality of buffer circuits connecting the peripheral buses of the circuit blocks to the main bus of the processor, wherein the first circuit blocks including the peripheral buses having connected thereto the axis-control circuits alone and the second circuit block with the other circuits each constitute separate package units.
Claim 2
Dependent Claim
118 words
An improved numerical control unit of the type which employs a plurality of control circuits and which performs data processing using a processor having a main bus connected thereto, wherein the improvement comprises: a plurality of first circuit blocks, each with a peripheral bus having connected thereto only axis-control circuits; a second circuit block with a peripheral bus having connected thereto circuits other than the axis-control circuits; and a plurality of buffer circuits connecting the peripheral buses of the circuit blocks to the main bus of the processor, wherein the first circuit blocks including the peripheral buses having connected thereto the axis-control circuits alone and the second circuit block with the other circuits each constitute separate package units.
Claim 3
Dependent Claim
16 words
The control unit of claim 1, wherein a main memory is connected to the main bus.
Claim 4
Dependent Claim
36 words
The control unit of claim 2, wherein the peripheral bus of the second circuit block is connected to at least a tape reader control circuit, a numerical control panel control circuit, and an input/output control circuit.
Claim 5
Dependent Claim
31 words
The control unit of claim 1, wherein said circuit blocks constituting package units each comprise a mother board having printed circuit boards connected thereto, said mother boards being connected by cables.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-09-25 | 1988-03-26 | 1988-09-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-09-25 | 1992-03-26 | 1992-09-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-09-25 | 1996-03-26 | 1996-09-25 | $7700.00 | Window Closed / Lapsed |