Data selector circuit with channel skipper for data acquisition system

Claim 2

In a data acquisition system, a data selection circuit for receiving information in the form of data signals on a plurality of input lines, and transmitting said information along an output line, comprising: multiplexer circuit means connected to said plurality of input lines for receiving data signals on said lines and individually connecting said input lines to an output line in response to sequencing signals; and timing circuit means connected to receive said data signals from said output line for producing and applying said sequencing signals to said multiplexer circuit means at time intervals which vary in dependence upon the signal level on said output line.

Claim 3

The data selection circuit as set forth in claim 1 wherein said timing circuit means comprises comparator circuit means for comparing the signal level on said output line with a reference value, and pulse producing circuit means responsive to said comparator means for producing a pulse having a first width when said signal level is above said reference value and producing a pulse having a second width when said signal level is below said reference value, said multiplexer circuit means being sequenced at time intervals dependent upon said pulse widths.

Claim 4

The data selection circuit as set forth in claim 2 wherein said timing circuit means further includes counter circuit means having an input receiving said pulses from said pulse producing circuit means and having an output connected to said multiplexer circuit means, wherein each time a pulse is received by said counter circuit means, a sequencing signal is sent to said multiplexer circuit means on the output of said counter circuit means.

Claim 5

The data selection circuit as set forth in claim 3 wherein said pulse producing circuit means includes a first monostable multivibrator for producing a pulse having said first pulse width, a second monostable multivibrator for producing a pulse having said second pulse width, and switch means responsive to said comparator means for actuating either said first multivibrator or said second multivibrator.

Claim 6

The data selection circuit as set forth in claim 4 wherein said pulse producing circuit means further includes a third monostable multivibrator having an output connected to an input of said switch means and having an input connected to receive the pulses from said first and second monostable multivibrators, and wherein said switch means is operative to connect the output of said third monostable multivibrator to the input of either said first monostable multivibrator or the input of said second monostable multivibrator in response to said comparator means.

Claim 7

A data selection circuit as set forth in claim 5 and further in combination with an acoustic detection system including: transmitter means for continuously ensonifying a sector of water with sonic energy varying in frequency between two frequency limits; receiver means for sensing echo frequencies and producing an output signal having a frequency which is related to the difference between a received echo frequency and a transmitted frequency; filter means for receiving the output signal of said receiver means and dividing it into a plurality of filter output signals, each of said filter output signals having a different frequency range; and display means for displaying said filter output signals, wherein said input lines connected to said multiplexer comprise said filter outputs, and said multiplexer output is connected to said display means, whereby said filter outputs are individually connected to said display means and displayed for time durations dependent on the signal content thereof.

Claim 8

The data acquisition circuit as set forth in claim 1 and further including display means connected to said multiplexer output for displaying the data signals received on said multiplexer output, said display means comprising a cathode ray tube having X, Y and Z axis inputs, said multiplexer output being applied to said Z axis input, and further wherein said timing circuit means is connected to circuitry for controlling said X and Y axis inputs such that said data signals received by said display means are displayed for time durations dependent upon the signal level thereof.