US4472686A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for reproducing and demodulating modulated digital signals
Assignee: Hitachi Ltd
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Filing: 1981-10-13
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Granted: 1984-09-18
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Expires: 2001-10-13
Abstract
Abstract A circuit for reproducing and demodulating a modulated digital signal which is modulated in a predetermined modulation system such as MFM, EFM and so on. A phase of a clock having a frequency multiplied by an integral number of a bit frequency of the modulated digital signal, is restricted or controlled by a signal showing that a predetermined pattern of the modulated digital signal occurred. The modulated digital signal is demodulated by the thus restricted clock to produce digital informations "0" and "1". A main requirement for detecting the predetermined pattern of the modulated digital signal, is that a reproduced modulated digital signal is reliable. In order to compensate for the drop-out of the modulated digital signal, the demodulation circuit is provided with a modulated digital signal reproducing circuit for complementing a predetermined signal pattern when the drop-out occurred.
Inventors
- 👤 Keizo Nishimura
- 👤 Hiroyuki Kimura
- 👤 Yasunori Kanazawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:02
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4904; H04L7/00; H04L7/0054; H04L7/0066; H04L7/04; H04L7/041; H04L7/042
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
209 words
A demodulation circuit for demodulating a modulated digital signal which is modulated under a certain modulation system in which the phase of the digital signal is inverted at predetermined intervals in accordance with a modulation rule depending on the successive values of the modulated data, comprising: a clock generator circuit for generating a clock signal having a frequency which is an integral multiple of the bit frequency of said modulated digital signal; at least one pattern detector means connected to receive said modulated digital signal for detecting whether said modulated digital signal is inverted correctly at a predetermined interval in accordance with said modulation rule of said modulated digital signal and for producing a discrimination signal in synchronism with said clock signal and in response to a detected predetermined pattern of signal values only when the phase of the modulated signal is correctly inverted; demodulating clock generator means connected to said pattern detector means for generating a demodulating clock signal which is restricted to a predetermined phase of said clock signal in response to said discrimination signal at the output of said pattern detector means; and demodulating means for demodulating said modulated digital signal to produce digital informations "0" and "1" at the timing of said demodulating clock signal.
Claim 2
Dependent Claim
209 words
A demodulation circuit for demodulating a modulated digital signal which is modulated under a certain modulation system in which the phase of the digital signal is inverted at predetermined intervals in accordance with a modulation rule depending on the successive values of the modulated data, comprising: a clock generator circuit for generating a clock signal having a frequency which is an integral multiple of the bit frequency of said modulated digital signal; at least one pattern detector means connected to receive said modulated digital signal for detecting whether said modulated digital signal is inverted correctly at a predetermined interval in accordance with said modulation rule of said modulated digital signal and for producing a discrimination signal in synchronism with said clock signal and in response to a detected predetermined pattern of signal values only when the phase of the modulated signal is correctly inverted; demodulating clock generator means connected to said pattern detector means for generating a demodulating clock signal which is restricted to a predetermined phase of said clock signal in response to said discrimination signal at the output of said pattern detector means; and demodulating means for demodulating said modulated digital signal to produce digital informations "0" and "1" at the timing of said demodulating clock signal.
Claim 3
Dependent Claim
61 words
A demodulation circuit as claimed in claim 1, wherein said pattern detector means comprises a shift register for shifting said modulated digital signal by said clock having the frequency which is an integral multiple of the bit frequency of said modulated digital signal, and a detector circuit for detecting a predetermined pattern of outputs at each stage of said shift register.
Claim 4
Dependent Claim
47 words
A demodulation circuit as claimed in claim 2, wherein said demodulating means includes means for demodulating said modulated digital signal to produce the digital informations "0" and "1" by comparing outputs at specific two output stages of said shift register, at the timing of said demodulating clock.
Claim 5
Dependent Claim
96 words
A demodulation circuit as claimed in claim 1, wherein said clock generator circuit comprises: a shift register for shifting said modulated digital signal by a reference clock having a frequency which is an integral multiple of the bit frequency of said modulated digital signal; a detector circuit for detecting a predetermined pattern of outputs at each output stage of said shift register; and a frequency divider for dividing said reference clock in response to an output signal of said detector circuit, to produce an output clock which serves as said clock of said clock generator circuit.
Claim 6
Dependent Claim
191 words
A demodulation circuit as claimed in claim 1, further comprising a modulated digital signal reproducing circuit which comprises: a signal drop-out detecting circuit for detecting the presence of signal drop-outs in said modulated digital signal; an inversion detecting circuit for detecting inverting points of said modulated digital signal; a signal drop-out duration detecting circuit for detecting duration of said signal drop-out on the basis of the output signals from said signal drop-out detecting circuit, and said inversion detecting circuit; a logic circuit for producing only the edge signal of said modulated digital signal which first appears after termination of said signal drop-out duration; a signal state discriminating circuit for producing the state of said modulated digital signal immediately before and after said signal drop-out; memory means for outputting a complementing digital signal pattern in accordance with a drop-out duration detection signal produced from said signal drop-out duration detecting circuit and an output signal produced from said signal state discriminating circuit; and a switching circuit of which operation is initiated by the edge signal produced from said logic circuit means for thereby outputting said complementing digital signal when said drop-out has occurred.
Claim 7
Dependent Claim
28 words
A demodulation circuit as claimed in claim 5, wherein said reproducing circuit comprises an error detector circuit for detecting whether said complementing digital signal is correct or not.
Claim 8
Dependent Claim
27 words
A demodulation circuit as claimed in claim 6, wherein said reproducing circuit comprises a plurality of said memory means and corresponding numbers of said error detector circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-09-18 | 1988-03-19 | 1988-09-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-09-18 | 1992-03-19 | 1992-09-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-09-18 | 1996-03-19 | 1996-09-18 | $7700.00 | Window Closed / Lapsed |