US4469449A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Drive system for electrochromic display cell
Assignee: Citizen Watch Co Ltd
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Filing: 1982-12-10
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Granted: 1984-09-04
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Expires: 2002-12-10
Abstract
Abstract A system for driving elements of an ECD cell, whereby each of at least two different color density states can be selectively designated for each element so that two different functions can be indicated by a single element. The selective designation is accomplished by comparing a command signal indicating the required current display state of an element with the contents of a memory circuit which stores the previous display state, the memory being capable of storing data representing at least two different display states. Any required change in the display state is thereby detected, and a predetermined amount of charge is accordingly supplied to or taken from the display element such as to produce the desired change in density state.
Inventors
- 👤 Toshikiyo Kato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:15
CPC Classifications
G; G04; G04G; G04G9/00; G04G9/0023; G04G9/0029; G04G9/0047; G09; G09G; G09G3/00; G09G3/04; G09G3/16; G09G3/19; G09G2340/00; G09G2340/16; G09G3/20; G09G3/2007; G09G3/2018
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
320 words
A drive system for an electrochromic display cell having a plurality of display segments, comprising: display data circuit means for producing display data signals corresponding to data to be displayed by at least one of said display segments; timing signal generating circuit means for producing a plurality of timing pulse signals including write timing pulse signals and erase timing pulse signals; converter circuit means coupled to receive said display data signals and responsive thereto for producing display data command signals to selectively designate a plurality of display density states of said display segment comprising at least a dark display density state and at least one grey display density state which is lower in density than said dark display density state; memory circuit means for memorizing said display data command signals from said converter circuit means and for producing corresponding memory signals; density change detection circuit means coupled to receive said memory signals from said memory circuit means and said display data command signals from said converter circuit means and responsive thereto for detecting changes in the display density state designated for said display segment by said display data command signals and for producing control signals in accordance with the results of said detection of changes; selector circuit means controlled by said control signals from said density change detection circuit means for selectively transferring specific pulses of said write timing pulse signals and said erase timing pulse signals to be output therefrom; a power source; drive circuit means controlled by said write timing pulse and erase timing pulse signals output from said selector circuit means for selectively supplying specific quantities of charge from said power source to said display segment and discharging said display segment by specific quantities of charge, to thereby selectively set said display segment into one of said plurality of display density states as designated by said display data command signals in accordance with said display data signals.
Claim 2
Dependent Claim
320 words
A drive system for an electrochromic display cell having a plurality of display segments, comprising: display data circuit means for producing display data signals corresponding to data to be displayed by at least one of said display segments; timing signal generating circuit means for producing a plurality of timing pulse signals including write timing pulse signals and erase timing pulse signals; converter circuit means coupled to receive said display data signals and responsive thereto for producing display data command signals to selectively designate a plurality of display density states of said display segment comprising at least a dark display density state and at least one grey display density state which is lower in density than said dark display density state; memory circuit means for memorizing said display data command signals from said converter circuit means and for producing corresponding memory signals; density change detection circuit means coupled to receive said memory signals from said memory circuit means and said display data command signals from said converter circuit means and responsive thereto for detecting changes in the display density state designated for said display segment by said display data command signals and for producing control signals in accordance with the results of said detection of changes; selector circuit means controlled by said control signals from said density change detection circuit means for selectively transferring specific pulses of said write timing pulse signals and said erase timing pulse signals to be output therefrom; a power source; drive circuit means controlled by said write timing pulse and erase timing pulse signals output from said selector circuit means for selectively supplying specific quantities of charge from said power source to said display segment and discharging said display segment by specific quantities of charge, to thereby selectively set said display segment into one of said plurality of display density states as designated by said display data command signals in accordance with said display data signals.
Claim 3
Dependent Claim
95 words
A drive system according to claim 1, in which said display data command signals from said converter circuit means selectively designate a clear display state, a grey display density state and a dark display density state of said display segment, and in which said memory circuit means comprise a first memory circuit comprising a bistable circuit for memorizing display data command signals which designate a dark display density state, and a second memory circuit comprising bistable circuits for selectively memorizing display data command signals designating said grey display density state and said clear display state.
Claim 4
Dependent Claim
42 words
A drive system according to claim 1, in which said memory circuit means comprise a bistable circuit for memorizing display data command signals selectively designating said grey display density state and said dark display density state produced by said converter circuit means.
Claim 5
Dependent Claim
98 words
A drive system according to claim 1, in which, in order to change said display segment from said dark display density state to said grey display density state in accordance with said display data signals, said selector circuit means is operative to first produce one of said display data command signals designating a clear display state and then one of said display data command signals which designates said grey display density state, whereby said display segment is momentarily set into said clear display state in the course of changing from said dark to said grey display density state.
Claim 6
Dependent Claim
67 words
A drive system according to claim 1, in which said display data circuit means comprise a timekeeping circuit coupled to receive timing signals from said timing signal generating circuit means for thereby computing time information and producing output signals indicative thereof as said display data signals, said timekeeping circuit comprising at least a minutes counter circuit and hours counter circuit for counting minutes and hours time information.
Claim 7
Dependent Claim
100 words
A drive system according to claim 5, in which said display data circuit comprises a plurality of timekeeping counter circuits, and in which said converter circuit means comprise a first group of gate circuits responsive to predetermined combinations of logic levels of timekeeping signals from said timekeeping counter circuits for producing display data command signals designating said dark display density state, and a second group of gate circuits responsive to predetermined combinations of logic levels of timekeeping signals from said timekeeping counter circuits for producing display data command signals selectively designating said clear display state and grey display density state.
Claim 8
Dependent Claim
75 words
A drive system according to claim 6, in which said timekeeping counter circuits comprise a seconds timekeeping counter circuit and a days timekeeping counter circuit, and in which said first gate circuit group comprises a group of AND gates and said second gate circuit group comprise a group of exclusive-OR gates, said first and second gate circuit groups being coupled to receive seconds and days timekeeping signals from said seconds and days timekeeping counter circuits.
Claim 9
Dependent Claim
78 words
A drive system according to claim 4, in which said timekeeping counter circuits comprise a minutes timekeeping counter circuit and an hours timekeeping counter circuit, and in which said first gate circuit group comprises a group of AND gates and said second gate circuit group comprise a group of exclusive-OR gates, said first and second gate circuit groups being coupled to receive minutes and hours timekeeping signals from said minutes timekeeping counter circuit and hours timekeeping counter circuit.
Claim 10
Dependent Claim
62 words
A drive system according to claim 1, in which said power source comprises a stabilized write voltage source, coupled to said display segments under the control of said write timing pulse segments from said selector circuit means and a stabilized erase voltage source, coupled to said display segments under the control of said erase timing pulse signals from said selector circuit means.
Claim 11
Dependent Claim
66 words
A drive system according to claim 1, in which said power source comprise a stabilized write current source, which is coupled to said display segments under the control of said write timing pulse signals from said selector circuit means and a stabilized erase current source, which is coupled to said display segments under the control of said erase timing pulse signals from said selector circuit means.
References Cited (Backward Citations)
US28199A
Cited
US3950936A
Cited
USRE28199E
Cited
US4034550A
Cited
US4057739A
Cited
US3987433A
Cited
US4205903A
Cited
US4077032A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-09-04 | 1988-03-05 | 1988-09-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-09-04 | 1992-03-05 | 1992-09-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-09-04 | 1996-03-05 | 1996-09-04 | $7700.00 | Window Closed / Lapsed |