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US4469274A Expired / Lapsed US ⏱️ 0.0 years remaining

Electronic thermostat with repetitive operation cycle

Assignee: Honeywell Inc
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Filing: 1982-02-19
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Granted: 1984-09-04
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Expires: 2002-02-19
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Abstract

Abstract An electronic multiple-setback thermostat for residential and commercial use includes an internal clock having a week-long cycle. The thermostat is programmed by the operator, usually manually actuable input devices, to control the furnace/air conditioning system to achieve a schedule of temperatures over the weekly period by simply inputting the temperature desired to be attained at the time of entry. Each temperature entry may be programmed to reoccur on a daily basis or to modify the program on a once-a-week basis. The thermostat employs an internal clock which controls memory addresses so that each memory location is representative of a short time period during the weekly cycle. A desired temperature signal is entered in a memory location determined by the clock state at the time of entry and is read out to the control system each time that time state reoccurs.The external temperature sensor employs a thermistor controlled oscillator that is used as the system clock source during failures of the primary power source.

Inventors

  • 👤 Michael R. Levine

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 04:07
CPC Classifications
F; F23; F23N; F23N5/00; F23N5/20; F23N5/203; G; G05; G05D; G05D23/00; G05D23/19; G05D23/1902; G05D23/1904; G05D23/20; G05D23/24

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 167 words
An electronic controller comprising: a clock operative to generate electrical signals representative of times within a repetitive time cycle and a repetitive subcycle which is a divisor of the cycle; a memory; input means, responsive to said clock, for entering set points into the memory; means, controlled by the clock, for reading set points out of the memory; means, controlled by the operator, for placing the system in a first mode wherein an inputted set point is stored in memory or in a second mode wherein a set point stored in the memory is recalled each time cycle; and means, for controlling the input means before the clock reaches a predetermined state, to store an inputted set point in a plurality of memory locations for recall at the same time during each clock subcycle, and for controlling the input means to store an inputted set point in a single memory location, after the clock reachs said predetermined state, for recall once in a plurality of clock subcycles.
Claim 2
Dependent Claim 167 words
An electronic controller comprising: a clock operative to generate electrical signals representative of times within a repetitive time cycle and a repetitive subcycle which is a divisor of the cycle; a memory; input means, responsive to said clock, for entering set points into the memory; means, controlled by the clock, for reading set points out of the memory; means, controlled by the operator, for placing the system in a first mode wherein an inputted set point is stored in memory or in a second mode wherein a set point stored in the memory is recalled each time cycle; and means, for controlling the input means before the clock reaches a predetermined state, to store an inputted set point in a plurality of memory locations for recall at the same time during each clock subcycle, and for controlling the input means to store an inputted set point in a single memory location, after the clock reachs said predetermined state, for recall once in a plurality of clock subcycles.
Claim 3
Dependent Claim 19 words
The system of claim 1 wherein said clock cycle is one week and the clock subcycle is one day.
Claim 4
Dependent Claim 24 words
The system of claim 1 in which said system has a third mode wherein the changes in said point are not entered into memory.
Claim 5
Dependent Claim 42 words
The system of claim 1 wherein the memory consists of a number of sections equal to the number of subcycles and a change in the set point is entered into each of the memory sections before the clock reaches said predetermined state.
Claim 6
Dependent Claim 112 words
A controller for a process, comprising: a clock operative to generate signals representative of time within a repetitive time cycle in terms of a particular division of the time cycle and of the time within each division; means for generating signals representative of a set point; a memory; and means for controlling the storage of set point signals in the memory in a first manner, in which a set point signal is recorded once for a clock cycle before the clock reaches a predetermined state, and in a second manner, in which a set point is recorded once for each division of the clock cycle, after the clock reaches said predetermined state.
Claim 7
Dependent Claim 112 words
A controller for a process, comprising: a clock operative to generate signals representative of time within a repetitive time cycle in terms of a particular division of the time cycle and of the time within each division; means for generating signals representative of a set point; a memory; and means for controlling the storage of set point signals in the memory in a first manner, in which a set point signal is recorded once for a clock cycle before the clock reaches a predetermined state, and in a second manner, in which a set point is recorded once for each division of the clock cycle, after the clock reaches said predetermined state.
Claim 8
Dependent Claim 21 words
The controller of claim 5 wherein said clock cycle consists of a week and a clock subcycle consists of a day.

References Cited (Backward Citations)

US4200910A Cited
US4235368A Cited
US4298163A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1987-09-04 1988-03-05 1988-09-04 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1991-09-04 1992-03-05 1992-09-04 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1995-09-04 1996-03-05 1996-09-04 $7700.00 Window Closed / Lapsed

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