US4468709A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dual-loop jitter correction circuit for correcting the time base error of an information signal
Assignee: Olympus Corp
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Filing: 1981-09-14
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Granted: 1984-08-28
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Expires: 2001-09-14
Abstract
Abstract In a jitter correction circuit for correcting a time base error caused in a color television signal readout from a video disc due to a fluctuation in a disc rotating speed and an eccentricity of the disc, a first closed loop control circuit includes a first phase difference detector for detecting a first phase deviation of a horizontal synchronizing signal of the color television signal and a first variable time constant lag filter for producing a first control signal in response to the first phase deviation and a second closed loop control circuit includes a second phase difference detector for detecting a second phase deviation of a color burst signal of the color television signal and a second variable time constant lag filter for producing a second control signal in response to the second phase deviation. When the first phase deviation is greater than a predetermined level, only the first control signal is supplied to a voltage controlled oscillator to produce clock pulses for driving a delay device formed by a number of charge coupled devices. When the first phase deviation is reduced to the predetermined level, a sum of the first and second control signals is supplied to the voltage controlled oscillator.
Inventors
- 👤 Hideyuki Kenjyo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:32
CPC Classifications
H; H04; H04N; H04N9/00; H04N9/79; H04N9/87; H04N9/89; H04N9/893
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
238 words
A jitter correction circuit for correcting a time base error of an information signal read out from an optical disc comprising: a variable delay device having a variable delay time for correcting the time base error of an information signal; a first closed loop control circuit having means for deriving a first synchronizing signal of a first frequency from an information signal, means for generating a first reference signal, means for detecting a first phase difference between the first synchronizing signal and the first reference signal, and means for adjusting the delay time of said variable delay device in accordance with the first detected phase difference to correct the time base error of the information signal; means for detecting said first phase difference and providing a control output when said phase difference is less than or equal to a predetermined value; and a second closed loop control circuit having means for deriving from the information signal a second synchronizing signal of a second frequency higher than said first frequency, means for generating a second reference signal, means for detecting a second phase difference between the second synchronizing signal and the second reference signal, and means responsive to said control output for adjusting the delay time of the variable delay device in accordance with the second detected phase difference to correct the time base error of the information signal, said predetermined value corresponding to a residual time base error.
Claim 2
Dependent Claim
238 words
A jitter correction circuit for correcting a time base error of an information signal read out from an optical disc comprising: a variable delay device having a variable delay time for correcting the time base error of an information signal; a first closed loop control circuit having means for deriving a first synchronizing signal of a first frequency from an information signal, means for generating a first reference signal, means for detecting a first phase difference between the first synchronizing signal and the first reference signal, and means for adjusting the delay time of said variable delay device in accordance with the first detected phase difference to correct the time base error of the information signal; means for detecting said first phase difference and providing a control output when said phase difference is less than or equal to a predetermined value; and a second closed loop control circuit having means for deriving from the information signal a second synchronizing signal of a second frequency higher than said first frequency, means for generating a second reference signal, means for detecting a second phase difference between the second synchronizing signal and the second reference signal, and means responsive to said control output for adjusting the delay time of the variable delay device in accordance with the second detected phase difference to correct the time base error of the information signal, said predetermined value corresponding to a residual time base error.
Claim 3
Dependent Claim
43 words
The circuit of claim 1 wherein said variable delay device comprises a voltage controlled oscillator for producing clock pulses and analog shift registers formed from charge coupled devices which are coupled to be driven by said clock pulses from said voltage controlled oscillator.
Claim 4
Dependent Claim
123 words
The circuit of claim 2 wherein said means for adjusting the delay time of the variable delay device in accordance with the first detected phase difference comprises a first variable time constant lag filter controlled by said first detected phase difference and coupled to said voltage controlled oscillator to provide a first control signal for adjusting the delay time of the variable delay device, and wherein said means for adjusting the delay time of the variable delay device in accordance with the second detected phase difference comprises a second variable time constant lag filter controlled by said second phase difference and coupled to said voltage controlled oscillator to provide a second control signal for adjusting the delay time of the variable delay device.
Claim 5
Dependent Claim
41 words
The circuit of claim 3 further comprising an adder coupled to receive and sum said first and second control signals for providing a third control signal to said voltage controlled oscillator for adjusting the delay time of the variable delay device.
Claim 6
Dependent Claim
37 words
The circuit of claim 4 wherein said means responsive to said control output comprises an analog switch responsive to said first phase difference decreasing to said predetermined value for coupling said second control signal to said adder.
Claim 7
Dependent Claim
62 words
The circuit of claim 3 wherein said means for deriving a first synchronizing signal comprises means for deriving a horizontal synchronizing signal from a television signal for use as said first synchronizing signal and wherein said means for driving a second synchronizing signal comprises means for deriving a color burst signal from said television signal for use as said second synchronizing signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-08-28 | 1988-02-27 | 1988-08-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-08-28 | 1992-02-27 | 1992-08-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-08-28 | 1996-02-27 | 1996-08-28 | $7700.00 | Window Closed / Lapsed |