US4465972A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Connection arrangement for printed circuit board testing apparatus
Assignee: Honeywell International Inc
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Filing: 1982-04-05
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Granted: 1984-08-14
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Expires: 2002-04-05
Abstract
Abstract Printed Circuit Board Testing Apparatus is disclosed which utilizes a "bed of nails" of contacts with conductive probes mounted in an insulating plate on a grid of 0.050 inch spacing to make a plurality of electrical contacts with a printed circuit board under test. This large number of contacts are all connected to the edge of a plurality of printed circuit boards mounted perpendicular to the back of the plate. Paths on each of these printed circuit boards electrically connect the probes of the contacts to a large scale integrated circuit chip on which are a plurality of analog switches each controlled by one bit of a binary word stored in a multi-stage shift register also on the chip. One side of each switch is connected to a probe while the other side of the switches are tied together in busses to create a multiplexing arrangement to thereby connect ones of the large number of probes to a relatively small number of input/output leads also connected to the printed circuit boards. In operation, selected ones of the analog switches on each chip are operated by serially loading binary words into the shift register on each chip to thereby operate switches and connect the board under test via the input/output leads to test circuitry.
Inventors
- 👤 James M. Sokolich
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 15:09
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2801; G01R31/2806; G01R31/2808; G01R1/00; G01R1/02; G01R1/06; G01R1/067; G01R1/073; G01R1/07392
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
346 words
An arrrangement for electrically connecting printed circuit boards under test to test apparatus, said connecting arrangement comprising: a plurality of conductive probes in a predetermined arrangement and placed against a printed circuit board under test to establish a plurality of electrical connections thereto; an insulating plate receiving the probes in said predetermined arrangement and capable of supporting the probes against ones of the printed circuit boards under test when said plurality of conductive probes are mounted in holes through the plate and extending out of either side of said plate; a plurality of first printed circuit board means mounted substantially perpendicular to said plate with one end of said contact probes being electrically connected to first conductive paths on said plurality of first board means; and integrated circuit means mounted to said first printed circuit board means and connected to said first conductive paths, the integrated circuit means connecting selected ones of said plurality of conductive probes to said testing apparatus to test electrical characteristics of said printed circuit board under test, the integrated circuit connecting means including a plurality of electronic switches organized into at least two groups with one side of each switch connected to a bus, and a multi-bit storage means wherein each bit location of said storage means is associated with at least one of said electronic switches, the binary number contents of a bit location of said storage means is used to control the operation of the associated switches, and a multi-bit binary number is placed in said stoage means to control the operation of said electronic switches, said integrated circuit means comprising individual integrated circuits on each of said plurality of first printed circuit boards, wherein said storage means comprises an individual storage means on each of said individual integrated circuits, and wherein said plurality of electronic switches comprises an individual plurality of electronic switches on each of said individual integrated circuits, said first conductive paths connecting said probes to said electronic switches which are selectively operated to connect said probes to said busses and thence to said testing apparatus.
Claim 2
Dependent Claim
346 words
An arrrangement for electrically connecting printed circuit boards under test to test apparatus, said connecting arrangement comprising: a plurality of conductive probes in a predetermined arrangement and placed against a printed circuit board under test to establish a plurality of electrical connections thereto; an insulating plate receiving the probes in said predetermined arrangement and capable of supporting the probes against ones of the printed circuit boards under test when said plurality of conductive probes are mounted in holes through the plate and extending out of either side of said plate; a plurality of first printed circuit board means mounted substantially perpendicular to said plate with one end of said contact probes being electrically connected to first conductive paths on said plurality of first board means; and integrated circuit means mounted to said first printed circuit board means and connected to said first conductive paths, the integrated circuit means connecting selected ones of said plurality of conductive probes to said testing apparatus to test electrical characteristics of said printed circuit board under test, the integrated circuit connecting means including a plurality of electronic switches organized into at least two groups with one side of each switch connected to a bus, and a multi-bit storage means wherein each bit location of said storage means is associated with at least one of said electronic switches, the binary number contents of a bit location of said storage means is used to control the operation of the associated switches, and a multi-bit binary number is placed in said stoage means to control the operation of said electronic switches, said integrated circuit means comprising individual integrated circuits on each of said plurality of first printed circuit boards, wherein said storage means comprises an individual storage means on each of said individual integrated circuits, and wherein said plurality of electronic switches comprises an individual plurality of electronic switches on each of said individual integrated circuits, said first conductive paths connecting said probes to said electronic switches which are selectively operated to connect said probes to said busses and thence to said testing apparatus.
Claim 3
Dependent Claim
78 words
The invention in accordance with claim 1 wherein said first printed circuit board means have second conductive paths connected to said busses and to said storage means and further comprising: ;p1 connector means for contacting said second conductive paths on said first printed circuit means, and second printed circuit board means on which said connector means are mounted and conductive paths on said second board means interconnect said connector means and connect said busses to said testing apparatus.
Claim 4
Dependent Claim
36 words
The invention in accordance with claim 2 wherein each of said individual storage means on each of said individual integrated circuits comprises a shift register into which a portion of said multi-bit binary number is stored.
Claim 5
Dependent Claim
33 words
The invention in accordance with claim 3 wherein all of said electronic switches comprise metallic oxide enhancement mode switches which provide analog switch operation to connect selected contact probes to said testing apparatus.
Claim 6
Dependent Claim
17 words
The invention in accordance with claim 4 wherein said plate is made of an electrical insulating material.
Claim 7
Dependent Claim
79 words
The invention in accordance with claim 1 wherein said integrated circuit means comprises: first switch means to establish the electrical connections between said conductive probes and said testing apparatus, and second switch means for establishing electrical connections to ones of said conductive probes when they are not placed against a printed circuit board under test, said last mentioned electrical connections being used in conjunction with said test apparatus to measure electrical characteristics of ones of said first switch means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-08-14 | 1988-02-13 | 1988-08-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-08-14 | 1992-02-13 | 1992-08-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-08-14 | 1996-02-13 | 1996-08-14 | $7700.00 | Window Closed / Lapsed |