Circuit for trimming FET differential pair offset voltage without increasing the offset voltage temperature coefficient

Claim 1

A circuit for trimming the offset voltage of a differential amplifier and reducing post-trim offset voltage drift, comprising: a pair of FET input transistors forming an input stage for a pair of inputs to said differential amplifier, each of said FET input transistors having a circuit-controllable drain-to-source current, the difference between said drain-to-source currents of said FET input transistors defining a drain-to-source current mismatch; an offset voltage of said differential amplifier being a function of said drain-to-source current mismatch and mismatches from among a plurality of non-controllable variables which characterize said FET, input transistors; and an offset adjustment circuit for trimming said offset voltage, said offset adjustment circuit comprising an initial trimming network having a low temperature coefficient for reducing said offset voltage and a temperature-dependent resistive network of a substantially higher temperature coefficient for causing said drain-to-source current mismatch to track the decrease in said mismatches in said non-controllable variables as the ambient temperature of said circuit increases, said decrease in said drain-to-source current mismatch serving to automatically reduce said post-trim offset voltage drift.